Vector table for CM0+ and CM4 in PSoC6

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cross mob
Anonymous
Not applicable

Hello,

I think two vector tables exist in PSoC6. One is for CM0+ and another is for CM4.

Basically, the initial address for cortex-M is placed from 0x0000_0000. User can offset the vector table by FW after CPU works. But the vector table have to be placed at 0x0000_0000 when it is at start up sequence.

By the way, PSoC6 has two cores. the both of CPUs must also have the vector tables which are different contents. In spite of two vector tables at same address, why does not PSoC6 happen any conflict?

Please let me know how PSoC6 is dealing with the vector table.

Best regards,

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1 Solution
AchimE_41
Employee
Employee
10 sign-ins 5 sign-ins First comment on KBA

Hello,

In PSoC6 you have two independent interrupt vector tables and also two interrupt controllers.

The reset is working because only the M0+ core will start at power-on/reset and the user code has to enable the CM4 core later.

The remapping of the CM4 vector table should happen somewhere in the startup code or when starting CM4 (haven't looked into that code yet).

kind regards,

Achim

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2 Replies
AchimE_41
Employee
Employee
10 sign-ins 5 sign-ins First comment on KBA

Hello,

In PSoC6 you have two independent interrupt vector tables and also two interrupt controllers.

The reset is working because only the M0+ core will start at power-on/reset and the user code has to enable the CM4 core later.

The remapping of the CM4 vector table should happen somewhere in the startup code or when starting CM4 (haven't looked into that code yet).

kind regards,

Achim

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StKr_1203736
Level 3
Level 3
First like received 10 replies posted 10 sign-ins

Perhaps you could offer an explanation of this:

StKr_1203736_0-1618859496073.png


PSoC Creator 4.4, Windoze 7, PDL 3.13, target CY8PROTO-063-BLE

 

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