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PSoC 6

MaFr_372266
New Contributor II

Can anyone help?  Looking for data spec / speed information on the cycle time to Read from Internal Flash to SRAM using MCU or DMA.

Looking to determine the fastest transfer speed for transferring a block of user data from the internal flash to SRAM cache.

Can currently only find data for Flash Writes.

Link to spec or TRM would be greatly appreciated.

Regards Mark.

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1 Solution
Alakananda_BG
Moderator
Moderator

Hi,

Here is the SYSCLK where you can set the speed depending on your application.

pastedImage_0.png

Regards

Alakananda

Alakananda

View solution in original post

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4 Replies
Alakananda_BG
Moderator
Moderator

Hi Mark,

The cycle time to Read from Internal Flash to SRAM using MCU or DMA depends on the rate at which SYSCLK is working, if it is more the the speed increases and vice versa.

Regards

Alakananda

Alakananda
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MaFr_372266
New Contributor II

Clarification how many system clock cycles; SYSCLK; to read from flash?

1: M4 CPU core for a single word of data, then for additional words of data, assume a single thread and no interruptions?

2: Using the DMA assuming the DMA channel has been configured except for the source address pointer.  Set source pointer address and then trigger DMA transfer. 

Looking for the fastest options in number of SYSCLK cycles.

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Alakananda_BG
Moderator
Moderator

Hi,

Here is the SYSCLK where you can set the speed depending on your application.

pastedImage_0.png

Regards

Alakananda

Alakananda

View solution in original post

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MaFr_372266
New Contributor II

Thanks for the reply but this is not what was being asked.  I already was aware of how to change the SYSCLK setting via creator and also via API's.  The question was and still is how many SYSCLK cycles are required to execute the code via MCU software control and also via hardware DMA transfer to move a Block of data from Flash to SRAM.

I a number of MCU TRM's there are details on the specific number of clock cycles required to move data from Flash to SRAM.

This is normally optimized to reflect the most efficient memory block transfer size.  This is the data we are looking to understand.

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