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PSoC™ 6

MB
Employee

Hello,
I am trying to set up a Dual-Core App on PSoC 6 BLE Prototyping Kit (CY8PROTO-063-BLE). While the Code on the M4 Core is currently only blinking the User LED on P6_3 i want the M0+ Core to send Data via SPI on SCB 1. The Code on the M0 Core is therefore initializing the SCB, GPIOs and Clocking and sends data and toggles another LED repeatedly. Unfortunately i can see the LEDs blinking (what means that both Cores are working) but the SPI does not send Data. 

This is the code running on the M0-Core:

 

#include "cy_pdl.h"

int main(void)
{

    /* Enable global interrupts */
    __enable_irq();

    /* Enable CM4. CY_CORTEX_M4_APPL_ADDR must be updated if CM4 memory layout is changed. */
    Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR);

    //---------------- Config GPIO for LED -----------------------------------

	cy_stc_gpio_pin_config_t pinConfig = {
		/*.outVal =*/ 1UL,                  /* Output = High */
		/*.driveMode =*/ CY_GPIO_DM_PULLUP, /* Resistive pull-up, input buffer on */
		/*.hsiom =*/ P7_1_GPIO,             /* Software controlled pin */
		/*.intEdge =*/ CY_GPIO_INTR_RISING, /* Rising edge interrupt */
		/*.intMask =*/ 1UL,                 /* Enable port interrupt for this pin */
		/*.vtrip =*/ CY_GPIO_VTRIP_CMOS,    /* CMOS voltage trip */
		/*.slewRate =*/ CY_GPIO_SLEW_FAST,  /* Fast slew rate */
		/*.driveSel =*/ CY_GPIO_DRIVE_FULL, /* Full drive strength */
		/*.vregEn =*/ 0UL,                  /* SIO-specific setting - ignored */
		/*.ibufMode =*/ 0UL,                /* SIO-specific setting - ignored */
		/*.vtripSel =*/ 0UL,                /* SIO-specific setting - ignored */
		/*.vrefSel =*/ 0UL,                 /* SIO-specific setting - ignored */
		/*.vohSel =*/ 0UL                   /* SIO-specific setting - ignored */
	};

	(void) Cy_GPIO_Pin_Init(P7_1_PORT, P7_1_NUM, &pinConfig);
	Cy_GPIO_Inv(P7_1_PORT, P7_1_NUM);


	/*************PDL*****************/

	/* Allocate context for SPI operation */
	cy_stc_scb_spi_context_t spiContext;

	/* Master configuration */
	cy_stc_scb_spi_config_t spiConfig_master =
	{
	.spiMode = CY_SCB_SPI_MASTER,
	.subMode = CY_SCB_SPI_MOTOROLA,
	.sclkMode = CY_SCB_SPI_CPHA0_CPOL0,
	.oversample = 10UL,
	.rxDataWidth = 8UL,
	.txDataWidth = 8UL,
	.enableMsbFirst = false,
	.enableInputFilter = false,
	.enableFreeRunSclk = false,
	.enableMisoLateSample = true,
	.enableTransferSeperation = false,
	.ssPolarity = CY_SCB_SPI_ACTIVE_LOW,
	.enableWakeFromSleep = false,
	.rxFifoTriggerLevel = 0UL,
	.rxFifoIntEnableMask = 0UL,
	.txFifoTriggerLevel = 0UL,
	.txFifoIntEnableMask = 0UL,
	.masterSlaveIntEnableMask = 0UL,
	};

	/* Assign pins for SPI master on SCB1: P10[0], P10[1], P10[2] and P10[3] */
	#define SPI_PORT_MASTER P10_0_PORT
	#define SPI_MOSI_NUM_MASTER P10_0_NUM
	#define SPI_MISO_NUM_MASTER P10_1_NUM
	#define SPI_SCLK_NUM_MASTER P10_2_NUM
	#define SPI_SS_NUM_MASTER P10_3_NUM
	

	/* Assign divider type and number for SPI */
	#define SPI_CLK_DIV_TYPE (CY_SYSCLK_DIV_8_BIT)
	#define SPI_CLK_DIV_NUM (0U)
	#define SPI_CLK_DIV_NUMBER_MASTER 5

	//Following is the settings for master

	(void) Cy_SCB_SPI_Init(SCB1, &spiConfig_master, &spiContext);

	/* Connect SCB1 SPI function to pins */
	Cy_GPIO_SetHSIOM(SPI_PORT_MASTER, SPI_MISO_NUM_MASTER, P10_1_SCB1_SPI_MISO);
	Cy_GPIO_SetHSIOM(SPI_PORT_MASTER, SPI_MOSI_NUM_MASTER, P10_0_SCB1_SPI_MOSI);
	Cy_GPIO_SetHSIOM(SPI_PORT_MASTER, SPI_SCLK_NUM_MASTER, P10_2_SCB1_SPI_CLK);
	Cy_GPIO_SetHSIOM(SPI_PORT_MASTER, SPI_SS_NUM_MASTER, P10_3_SCB1_SPI_SELECT0 );

	/* Configure SCB1 pins for SPI Master operation */
	Cy_GPIO_SetDrivemode(SPI_PORT_MASTER, SPI_MISO_NUM_MASTER, CY_GPIO_DM_HIGHZ);
	Cy_GPIO_SetDrivemode(SPI_PORT_MASTER, SPI_MOSI_NUM_MASTER, CY_GPIO_DM_STRONG_IN_OFF);
	Cy_GPIO_SetDrivemode(SPI_PORT_MASTER, SPI_SCLK_NUM_MASTER, CY_GPIO_DM_STRONG_IN_OFF);
	Cy_GPIO_SetDrivemode(SPI_PORT_MASTER, SPI_SS_NUM_MASTER, CY_GPIO_DM_STRONG_IN_OFF);


	/* Connect assigned divider to be a clock source for SPI */
	Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUM);

	/* SPI master desired data rate is 1 Mbps.
	* The SPI master data rate = (clk_scb / Oversample).
	* For clk_peri = 50 MHz, select divider value 5 and get SCB clock = (50 MHz / 5) = 10 MHz.
	* Select Oversample = 10. These setting results SPI data rate = 10 MHz / 10 = 1 Mbps.
	*/
	Cy_SysClk_PeriphSetDivider (SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUMBER_MASTER, 4UL);
	Cy_SysClk_PeriphEnableDivider(SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUMBER_MASTER);

	/* Enable SPI to operate */
	Cy_SCB_SPI_Enable(SCB1);

    for (;;)
    {
    	(void) Cy_SCB_SPI_Write(SCB1,0x9F);
    	Cy_GPIO_Inv(P7_1_PORT, P7_1_NUM);
    	Cy_SysLib_Delay(1023);
    }
}

 

 

Does anyone have an idea on how to fix this?

Best regards,
Marius 

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1 Solution
VenkataD_41
Moderator
Moderator

Hi Marius,

1. Please go through the Low-Level/High-level SPI Master code example for PSoC 6 in PSoC Creator and follow the same firmware guidelines and check once.

2. Please check the pin numbers and whether they are configured properly.

3. Please use the same length of wires for all the SPI lines.

Thanks and regards

Ganesh

View solution in original post

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1 Reply
VenkataD_41
Moderator
Moderator

Hi Marius,

1. Please go through the Low-Level/High-level SPI Master code example for PSoC 6 in PSoC Creator and follow the same firmware guidelines and check once.

2. Please check the pin numbers and whether they are configured properly.

3. Please use the same length of wires for all the SPI lines.

Thanks and regards

Ganesh

View solution in original post

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