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PSoC 6

MiAb_4832311
New Contributor II

I'm hoping that someone would be able to take a look at a schematic for a custom PSoC 6 design (using the CY8C6245 chip) to verify that our design is implemented correctly (schematic PDF attached). A couple things in particular that I was hoping someone with more experience designing around this system could look at:

  • We're planning on using the programming header (J1) connected to a MiniProg device, but are wondering if there's some way to use the USB connection for programming in addition/instead. Should we be connecting this to VDDD or to VTARG? 
  •  The connection the eMMC chip (U2)
  •  Our use of decoupling capacitors
  • The overall connections of the PSoC chip to the power rails
  •  One of our design requirements is to be able to access the eMMC chip as a storage device over USB, should this be feasible given the design and the capabilities of the PSoC chip we are using?

Thanks in advance!

 

 

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Aashita_Raj
Moderator
Moderator

Hi @MiAb_4832311 ,

I went through your attached schematics pdf and these are the following comments, I would like to make-

1. For programming and debugging of CY8C6245, you can use external debugger such as MiniProg via any connector supported by the debugger. We do not recommend to use USB for programming. The serial wire debug (SWD) or the JTAG interface can be used as the program/debug protocol between the external device and PSoC 6 MCU. In addition, PSoC 6 MCU supports Arm Embedded Trace Macrocell (ETM) on the Cortex-M4 CPU.

2. For this, I would suggest you to kindly refer "Secure Digital Host Controller" section of the Hardware Design Considerations . It is recommended to have pull-up resistors  in the range of 10 kΩ – 100 kΩ on the SDIO lines. Also, it is recommended to use series termination resistor of 33 Ω on the SDIOs lines. I see that your have used pull-up resistors of 10 kΩ on the SDIO lines. Kindly check for the termination resistor in your connection.

3. After comparing with the schematics given here , I see that the values provided are same as the ones given in the link. Can you please let me know the reason for using 2.2uF cap, since our schematics use 0.22uF capacitors over the kit board? Please let me know if this information helps you or if in case I am missing some interpretation here.

4. I would recommend you going through the "Power" section and appendix "Schematic Checklist" of Hardware design requirements. I see that there are a few mismatches for the capacitor values for VCCD pin, which does not satisfy the schematic checklist for power. Also, your connection for  VBACKUP which is connected to a coin cell is according to the recommendation. All the other power pin connections seem to be correct. I would still ask you to tally the decoupling capacitor values once for the overall best working.

5. Yes! The SDHC driver on PSoC6 can be used for the eMMC interface. Please refer the details on SDHC here . I would suggest you to go through this code example, which uses the emFile middleware library that includes emFile in the form of pre-built libraries along with the hardware layer and OS layer implementations for PSoC 6 MCUs. The storage device can be either an SD card or a QSPI NOR flash. EmFile is the driver used to interact with SD, eMMC, nor/nand flashes etc.

I hope this helps with your requirements. Please reach out to us in case of any further clarifications.

Best Regards,

Aashita

 

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4 Replies
Aashita_Raj
Moderator
Moderator

Hi @MiAb_4832311 ,

I went through your attached schematics pdf and these are the following comments, I would like to make-

1. For programming and debugging of CY8C6245, you can use external debugger such as MiniProg via any connector supported by the debugger. We do not recommend to use USB for programming. The serial wire debug (SWD) or the JTAG interface can be used as the program/debug protocol between the external device and PSoC 6 MCU. In addition, PSoC 6 MCU supports Arm Embedded Trace Macrocell (ETM) on the Cortex-M4 CPU.

2. For this, I would suggest you to kindly refer "Secure Digital Host Controller" section of the Hardware Design Considerations . It is recommended to have pull-up resistors  in the range of 10 kΩ – 100 kΩ on the SDIO lines. Also, it is recommended to use series termination resistor of 33 Ω on the SDIOs lines. I see that your have used pull-up resistors of 10 kΩ on the SDIO lines. Kindly check for the termination resistor in your connection.

3. After comparing with the schematics given here , I see that the values provided are same as the ones given in the link. Can you please let me know the reason for using 2.2uF cap, since our schematics use 0.22uF capacitors over the kit board? Please let me know if this information helps you or if in case I am missing some interpretation here.

4. I would recommend you going through the "Power" section and appendix "Schematic Checklist" of Hardware design requirements. I see that there are a few mismatches for the capacitor values for VCCD pin, which does not satisfy the schematic checklist for power. Also, your connection for  VBACKUP which is connected to a coin cell is according to the recommendation. All the other power pin connections seem to be correct. I would still ask you to tally the decoupling capacitor values once for the overall best working.

5. Yes! The SDHC driver on PSoC6 can be used for the eMMC interface. Please refer the details on SDHC here . I would suggest you to go through this code example, which uses the emFile middleware library that includes emFile in the form of pre-built libraries along with the hardware layer and OS layer implementations for PSoC 6 MCUs. The storage device can be either an SD card or a QSPI NOR flash. EmFile is the driver used to interact with SD, eMMC, nor/nand flashes etc.

I hope this helps with your requirements. Please reach out to us in case of any further clarifications.

Best Regards,

Aashita

 

View solution in original post

MiAb_4832311
New Contributor II

Thanks @Aashita_Raj,

Thanks for reviewing the schematics! Very glad to hear that it looks like most of it is set up correctly. I'm not sure why I put in 2.2uF caps instead of 0.22uF -- I probably misread the schematic when I was initially setting things up. What mismatches did you see for the VCCD pin? Looking between the CY8CPROTO-062S-4343W schematic and the Hardware Design Considerations, it looks like it uses a 4.7uF and 1uF capacitor in parallel, and a 2.2uH inductor across VCCD-VIND. Am I missing something else? Everything else makes sense to me -- I'll add in those series termination resistors, and double check all the other decoupling capacitors.

 

One other question -- for the SWD programming interface, which power rail should be connected as the supply there? Should VTARG be connected to VDDD? (Right now,  VTARG is connected to the 3.3V regulated supply, on the non-PSoC side of the ferrite beads).

 

Thanks for the help!

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MiAb_4832311
New Contributor II

@Aashita_Raj as I'm looking back over the schematic, I'm not sure which 2.2uF capacitors you're referring to -- C1, C5, and C7 are for the eMMC memory chip (from the datasheet for that device), C22, C26, and C7 are for the PMIC, and C54 is for the coin cell recharge circuit. 

I think I got most of my decoupling capacitor values from the CY8CMOD-062S3-4343W schematic, rather than the CY8CPROTO board. I think my logic was that the PROTO board was the carrier, so additional decoupling was needed between the loaded module and the main proto board, but let me know if that logic is incorrect. Do I need the additional decoupling capacitors loaded in the proto board? They aren't described in the Hardware Design Considerations document, either.

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Aashita_Raj
Moderator
Moderator

Hi @MiAb_4832311 ,

1. For SWD programming interface, the VTARG should be connected to VDDD. I have shared an image from the hardware design considerations to show this as below-

Aashita_Raj_0-1628181259807.png

2. For the VCCD pin, I checked once again. I am sorry for my mistake. Yes! I can see the connection for the 4.7 uF capacitor which I thought was missing earlier.

3. Regarding the 2.2uF capacitor, I see that you are following cy8cmod-062s3-4343w_schematics so the capacitors value seem to be correct then. And also regarding your query in your last response, I am checking with my team internally if I could get you a proper answer to that. I would appreciate your patience and time with this.

Best Regards,

Aashita

 

 

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