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I'm looking for ways to ease the chip from some combinatorial logic. I have 4 instances of a component that has a 4-input OR gate, and I'm tempted to remove that OR gate by moving it into a datapath. I'd use parallel in, and use the all-zero detector (inverted) to see if any bit is set - if that is feasible at all. Would that use less PLD resources than a 4-input OR gate? the number of signals (4 in, 1 out) is the same, but does it "free the way" for other parts of a larger design?
Also, could this be combined with a memory-to-hardware latch (D register to accumulator to parallel out)?
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Hello ChRe_4711096
You can have a look at the PLD Packing summary in the .rpt file under the Results tab. The PLD packing summary provides the number of PLDs available, Used and Free. The project attached by you in the previous response not require any PLD.
In order to find out the resources utilized in both the cases you can look at the Resource meter in the PSoC Creator. The Resource Creator updates only after you build the project.
Best Regards
Ekta
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Hello ChRe_4711096
You can have a look at the PLD Packing summary in the .rpt file under the Results tab. The PLD packing summary provides the number of PLDs available, Used and Free. The project attached by you in the previous response not require any PLD.
In order to find out the resources utilized in both the cases you can look at the Resource meter in the PSoC Creator. The Resource Creator updates only after you build the project.
Best Regards
Ekta