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PSoC™ 6

ChRe_4711096
New Contributor II

I'm looking for ways to ease the chip from some combinatorial logic. I have 4 instances of a component that has a 4-input OR gate, and I'm tempted to remove that OR gate by moving it into a datapath. I'd use parallel in, and use the all-zero detector (inverted) to see if any bit is set - if that is feasible at all. Would that use less PLD resources than a 4-input OR gate? the number of signals (4 in, 1 out) is the same, but does it "free the way" for other parts of a larger design?

Also, could this be combined with a memory-to-hardware latch (D register to accumulator to parallel out)?

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1 Solution
Ekta
Moderator
Moderator

Hello ChRe_4711096

You can have a look at the PLD Packing summary in the .rpt file under the Results tab. The PLD packing summary provides the number of PLDs available, Used and Free. The project attached by you in the previous response not require any PLD.

pastedImage_0.png

In order to find out the resources utilized in both the cases you can look at the Resource meter in the PSoC Creator. The Resource Creator updates only after you build the project.

pastedImage_5.png

Best Regards

Ekta

View solution in original post

2 Replies
ChRe_4711096
New Contributor II

The attached project has a UDB component that seems to do the trick, but I'm not sure if it's more efficient than a PLD OR gate in a larger design. Probably also highly depends on the case at hand.

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Ekta
Moderator
Moderator

Hello ChRe_4711096

You can have a look at the PLD Packing summary in the .rpt file under the Results tab. The PLD packing summary provides the number of PLDs available, Used and Free. The project attached by you in the previous response not require any PLD.

pastedImage_0.png

In order to find out the resources utilized in both the cases you can look at the Resource meter in the PSoC Creator. The Resource Creator updates only after you build the project.

pastedImage_5.png

Best Regards

Ekta

View solution in original post

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