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PSoC™ 6 Forum Discussions

RaMu_4639021
Level 1
5 replies posted 5 sign-ins First reply posted
Level 1

We are using I2C Master High Level APIs with registered callback to notify the transaction complete. Everything works fine when MCU is awake. When sleep is enabled MCU goes to sleep after initiating transaction, the I2C callback doesn't seem to happen. Eventually the transactions completes successfully when MCU wakes-up for other wake-up reasons but it takes in order of seconds to complete the transactions.

We are using freeRTOS tickless sleep to sleep during the transaction.

Here is the code snippet. Please let me know if you see anything wrong with our approach.

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Hari
Moderator
Moderator 750 replies posted 500 replies posted 250 solutions authored
Moderator

Hi RaMu_4639021

The I2C master does not generate an interrupt for a transaction. The interrupt is triggered based on the write or read conditions after the command is sent to the master. So, you need to have an alternate wakeup source when you want the master to send the data to the slave.

You could use a WDT to wake it up periodically.

Best regards,
Hari

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RaMu_4639021
Level 1
5 replies posted 5 sign-ins First reply posted
Level 1

Hey Hari,

Not sure I follow completely. As per the PSOC the Cy_SCB_I2C_MasterWrite automatically write entire buffer using Cy_SCB_I2C_Interrupt. We are going SLEEP after return of Cy_SCB_I2C_MasterWrite and expecting Cy_SCB_I2C_Interrupt to wakeup the MCU to send remaining bytes until the CY_SCB_I2C_MASTER_WR_CMPLT_EVENT.

Are you saying Cy_SCB_I2C_Interrupt won't trigger on its own?

/*******************************************************************************

* Function Name: Cy_SCB_I2C_MasterWrite

****************************************************************************//**

*

* This function configures the master to automatically write an entire buffer

* of data to a slave device. After the transaction is initiated by this

* function it returns and \ref Cy_SCB_I2C_Interrupt manages further data

* transfer.

*

* When a write transaction is completed (requested number of bytes are written

* or error occurred) the \ref CY_SCB_I2C_MASTER_BUSY status is cleared and

* the \ref CY_SCB_I2C_MASTER_WR_CMPLT_EVENT event is generated.

*

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Hari
Moderator
Moderator 750 replies posted 500 replies posted 250 solutions authored
Moderator

Hello RaMu_4639021

In your application, what is the tickless sleep mode that you set? Is it sleep or deepsleep? I2C component will be able to wake the CPU up due to an interrupt if the idle mode is sleep. However, under DeepSleep conditions, I2C cannot wake the CPU.

Best regards,
Hari

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RaMu_4639021
Level 1
5 replies posted 5 sign-ins First reply posted
Level 1

Hey Hari,

We are using the SLEEP during the i2c transactions. We choose between DEEPSLEEP and SLEEP based on power constraints.

By using logic analyzer we figured out that its not wakeup issue. If i2c interrupt occurs between the sleep check to actual sleep then system goes to sleep after processing interrupt, so stays in sleep until the next wakeup. The i2c seem to work if disable and enable the interrupts as per Tickless Low power features in FreeRTOS, but the new problem is, now system not responding to  ​MCWDT interrupts. System is not waking from DEEPSLEEP without interrupt enabled.

The Cy_SysPm_DeepSleep does _WFI instruction in critical section and BLE seems wakeup from DEEPSLEEP even with interrupt disabled.

Do we need to have interrupts enabled to use MCWDT as DEEPSLEEP wakeup source?

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Hari
Moderator
Moderator 750 replies posted 500 replies posted 250 solutions authored
Moderator

Hi RaMu_4639021

Can you please share your new vApplicationSleep function? How are you disabling the interrupts? If you use critical sections, MCWDT will still be able to wake the device from deepsleep.

Note that you must not disable the interrupt using NVIC_DisableIRQ as the interrupts will be completely disabled instead of masking and will not wake the CPU from low power mode.

Best regards,
Hari

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