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PSoC™ 6

BeTu_3769071
New Contributor II

Hello,

I'm working on a new design using the CY8CKIT-062-WiFi-BT as a reference. I've noticed with this chip that it's using pins P2_0 to P2_5 as an SDIO interface for the onboard WiFi module. Looking at the documentation however I'm confused as to how these pins are configured. The datasheet makes no mention of SDHC support, and the architecture technical reference manual has one reference in the errata to an SDHC chapter that looks like it no longer exists. The table at this link https://www.cypress.com/documentation/datasheets/psoc-6-mcu-cy8c62x6-cy8c62x7-datasheet also says that there is no SDHC support.

What exactly is happening on this development board? From available documentation it looks like there is SDHC support, however the development board does appear to work.

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RaktimR_11
Moderator
Moderator

Hello,

Sorry for the delayed response on this. CY8C6247 does not have a dedicated SDHC support; instead SDIO host controller was implemented using UDBs. I hope now the CY8CKIT-062 kit operation makes sense.

Instead, I would recommend using CY8C62x8, CY8C62xA family in your new design which has dedicated SDHC interface for you to interface the WiFi/BT solutions from Cypress. Reference kit: https://www.cypress.com/documentation/development-kitsboards/psoc-6-wi-fi-bt-prototyping-kit-cy8cpro...

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RaktimR_11
Moderator
Moderator

Hello,

Sorry for the delayed response on this. CY8C6247 does not have a dedicated SDHC support; instead SDIO host controller was implemented using UDBs. I hope now the CY8CKIT-062 kit operation makes sense.

Instead, I would recommend using CY8C62x8, CY8C62xA family in your new design which has dedicated SDHC interface for you to interface the WiFi/BT solutions from Cypress. Reference kit: https://www.cypress.com/documentation/development-kitsboards/psoc-6-wi-fi-bt-prototyping-kit-cy8cpro...

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