I am planning on using CY8C6246BZI-D04 as the main MCU for my application. I am planning on using the 80-WLP type. The pitch of this 0.34-0.35 mm (shown below). What is the typical recommended via size for this kind of pitches?
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PSoC 6 MCU
Thanks for pointing it out. I meant CY8C6247FDI-D02. Space is very critical in our application, so we have to use the smallest package. Would it be feasible to use 3/6 mil or 3.5/7 mil via? Will it be manufacturable easily?
If I use the 4/10 mil via as suggested then the clearance between two adjacent vias will be about 1.7-2 mil. Won't this make the design hard to manufacture? Or is this easier to manufacture compared to having smaller vias such as 3/6 mil?
Thanks & Regards
Thanks for the suggestion! We ended up using 4/8 mil via itself. Unfortunately we had use layer-2 as well for routing which cut off ground references to some of the tracks. Hopefully it will still be functional.