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PSoC™ 6

ChRe_4711096
New Contributor II

My design is using almost all I/O of the 124-pin BGA package (76/87, or 88%) and depending on where I drop pins I get different timing analysis and PLD packing results. There will be some software controlled pins as well, but most are controlled by UDBs or SCBs and some are analog with their own restrictions. Is there a way to make life easier for the toolchain by picking pins that are (probably) easy to route to from a UDB? Or, putting it differently, are certain UDBs closer to certain ports than others? I know that the possibilities to re-route SCBs are very limited, but there should be an optimal solution for the rest.

There are obvious and documented limitations in the analog routing, where I had to place a few pins on certain AMuxBus segments to help find a solution. Does such a strategy exist for the digital part as well?

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1 Solution
Vison_Zhang
Moderator
Moderator

The best way to get optimal UDB routing is unlock the digital pins which connects UDB resource, let Creator digital resource assignment algorithm find the best digital routing solution. You can do minor adjustment based on your requirement on the pin assignment generated by Creator.

View solution in original post

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4 Replies
Len_CONSULTRON
Honored Contributor II

ChRe,

As you pointed out, the SCBs have limited routing.

Usually the best way to get optimal UDB and SCB roiting is NOT to lock the pins.   Let Creator auto-assign the IO pins assigned if possible.

This means the board layout should be done after the project is built.

Len

Len
"Engineering is an Art. The Art of Compromise."
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ChRe_4711096
New Contributor II

Well, my design is past the point where PSoC creator can come up with a solution for pin placement just on its own. It needs some pins locked in order to get through analog routing (is there a "softer" way of putting a group of 4 pins on the same AMuxBus segment?), and at that point I must know if I'm making the digital part harder than necessary or not. Even when I do that, the suggested pins for the digital parts are might be feasible from PSoC Creator's point of view but absolutely crazy for board layout.

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Len_CONSULTRON
Honored Contributor II

ChRe,

With the PSoC6 fixed function blocks (TCPWMs. SCBs, and others) , it was elected to almost hard-code the pins to the block functions being used.   This is because the PSoC devices with a much more flexible digital routing method can be prone to reduced operating frequencies because of accumulative UDB and datapath propagation delays.

With analog, I don't know a 'softer' way to force the auto-selection of pins using the same AMuxBus.

Len

Len
"Engineering is an Art. The Art of Compromise."
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Vison_Zhang
Moderator
Moderator

The best way to get optimal UDB routing is unlock the digital pins which connects UDB resource, let Creator digital resource assignment algorithm find the best digital routing solution. You can do minor adjustment based on your requirement on the pin assignment generated by Creator.

View solution in original post

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