I have some problems when I try to implement a project with amplifiers. the PSoC is CY8C29466, the input is a dc voltage from 0 to 15mv from a sensor, I want to achieve an output in the range 0 to 5V.
I selected a 3 op-amps and set the gain. however when I want to add a PGA after the INSAMP I find it seems impossible, can anybody tell me how to do that? btw, if i use a 2 op-amps it's possible...
the second problem is about the AGND, as is showed in the data sheet, the AGND is Vdd/2, and also can be set by the parameter ref mux in the global resource. since my interest signal is alwasy positive, so I tried to set Vss as reference voltage for 2 op-amp INSAMP and PGA, but the noise is quite big and I even can't observe the output signal...what's more, this method is impossible for 3 op-amp INSAMP. so I want to know may I set the "ref mux" p2+/-p2 then connect p24 to GND and p26 to VSS?
thank you for your help!
is it possible conect insamp to pga internally?
insamp output fets pga input but when i do it, the result isnt Valuable.
and when they conect externaly output have lots of noise.
how can i reduse the noise?or can it conect internaly?
insam is 3 op_amp.
You can reduce noise on analog ground reference by enabling that in Global settings,
that commits P2(4) to use as a pin to place a capacitor on.
Set OpAmp an Analog Buffer to high power in global settings.
Some useful references when doing low nosie, high precision designs.
1) Start by using scope on infinite persistence, and look at supply rails to see how much
pk-pk noise you have. Then look at noise BW with a spectrum to see what major contributing components are.
2) When you run A/D consider shutting off other timer/counters to reduce noise contributors.
3) Same as 2, if driving hi current loads like LEDs, 7 seg displays, heavy C loads, shut that I/O activity off.
4) Not all capacitors are equal. Look at actual Z vs f curves. Polymer tantalums for bulk much better than electrolytic or regular tantalums. Use caps with low lead L. Bypass always with bulk + ceramic s(.1 and .01 uF).
5) Split grounds and analog grounds and rejoin as close to power source as possible.
6) Scope on infinite persistence, look at clock oscillator phase noise to establish if excessive.
7) Band limit the signal chain.
😎 Use external reference ground/bypass cap.
9) Reduce hi-z nodes to low z where possible to minimize noise pickup.
10) Some references
I set up attached project, PGA G = 1, IA G = 2, Inv input grounded, NI attached to
DAC9, fed a ramp via DAC9 to IA, and looked at PGA out. Run on a PSOCeval1
board. What one observes is a fair amount of noise, ~ 1/2 volt. I looked at Vcc
on the board, scope on infinite persistence, also saw 1/2 volt of noise there.
Note this was running via ICE CUBE which may also be contributing a lot of noise.
So I went to Miniprog and noise dropped to ~ 100 mV, board still pretty noisey.
Noise is specific to you layout to a major extent, and signal averaging/filtering should
help remaining issues.
This ap note shows how to bring COM out to a pin. Note you
would have to buffer that, load it, with a very high Z load to
insure you do not change theCOM value of the idealized
Only 3 OA design for IA allows you to bring out COM.
i use cy8c29466-24sxi and i have problem whit extrakting commen mode signal
howe can i conect a output pin or buffer to insamp-3?
it dosnt any wire .
perhaps i must write c cod but i dont know how?
pleas help me.
Looking at Datasheet you can output either the IA diff out voltage, or the CM voltage, and
setup is discussed as follows -
This parameter only applies to the three opamp topology. The common mode node connects the two continuous time blocks at the “ends” of their resistor strings (see the figure “Three Op-Amp Instrumentation Amplifier Simplified Schematic”). The common mode voltage derived from this node is useful in many applications for improving noise immunity through shielding by such means as guard traces. This voltage may be connected to the analog column output bus and its associated analog output buffer through either of the CT PSoC blocks, INV or NON_INV, by setting this parameter. In addition to these two options, the CommonModeOut parameter may be set to “None.”
One of the two CT blocks, either INV or NON_INV, will lie in the same analog column as the switched capacitor CONVERT block. If the AnalogBus parameter is set to Enable, either set CommonModeOut to “None” or set it to the block that lies in the column not shared by the CONVERT block. Otherwise, the output of the INSAMP will be connected in a feedback loop to the common mode point and the output behavior will not correspond to expectations.
However, I would advise you post a tech case at www.cypress.com, as I do not consider myself an expert at PSOC 1 Routing, seems odd to me you would not be able to get both DM and CM signals out to a pin. Do the forum a favor, if you get an answer post on your thread the results.
The IA, 3 OpAmp, takes two CT blocks, and one sw cap block. Translate
only one column clock matters, that of the CONVERT block. Datasheet
does not indicate any need to use same clock for both columns.
Clock is required only for SC block of instrumentation amplifier (IA). CT blocks do not require any clock except in the case of comparator implementation where clock is used for latching the output.
As far as common mode output routing is concerned, it requires ABUS output resource. If you are routing difference output (SC block output) to a pin, it will consume ABUS resource of the column where SC block is placed. Choose a CommonModeOut option so as to select a column different from a SC block one. In this way, you will be able to route both difference and common mode.
This common mode connection doesn't show up in device editor. But you can check register ACBxxCR3 bit 3 in PSoCConfigTBL.asm file. If this bit is set to 1, it means, Common mode output is connected to ABUS. For more details of this register, see technical reference manual of the device.
Also, make sure to enable column output buffer to route the ABUS output to pin.