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PSoC™ 5, 3 & 1

Anonymous
Not applicable

Hi:

   

As my experiment on EZI2C.

   

1) PSoC3 I2C_CSR.bit3 (address)  (0x49d7) was descripted in TRM as be cleared by firmware writing '0'.

   

But in EZI2C_INT.c generated by creator,  ISR function never write this bit  '0' to clear it.   Is this bit will be cleared by any accessing instead of writing '0' ?

   

2) The I2C interrupt mask never be mentioned in TRM, it seems built in UDB, is it?  If any MASK register exist, what's the initial/reset value, since I have not found any configuration in EZI2C_Start().

   

 

   

Thanks

   

B.R

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3 Replies
Anonymous
Not applicable

Oh, I have checked question 2, the mask is actually in CFG register.

   

But are the address match & byte complete interrupt is none-mask interrupt? Since no mask for them.

   

Thanks.

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ToddD_41
Employee

1)PSoC3 I2C_CSR.bit3 (address)  (0x49d7) was descripted in TRM as be cleared by firmware writing '0'.

   

But in EZI2C_INT.c generated by creator,  ISR function never write this bit  '0' to clear it.   Is this bit will be cleared by any accessing instead of writing '0' ?

   

 

   

This bit is cleared in the EzI2C Interrupt routine. If you look at lines 301 and 319 of the ISR you will see that the CSR register is written to. In these writes the address bit is not written with a 1, so it is cleared.

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Anonymous
Not applicable

Oh, yeh, I see. 

   

So how about the address match & byte complete interrupt? They are non-mask?

   

Thanks for the reply.

   

B.R

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