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PSoC™ 5, 3 & 1

prbh_3338016
Contributor

Dear Guru's,

Need your immediate help on power supply section of psoc 5LP. I have develop the datalogger  project using kit 59 . now i want to develop the printed circuit boards. I have gone through datasheet and application notes of power section. But i got confused regarding the unregulated and regulated design. Some how i am not able to get the concept.

I need 5 volt working also scope for dedicated usb i/o in future

I need to know which power supply method is good for 20 bit adc performance. Also Please guide me with the schematic .

(1)What does unregulated method means

(2)what does regulated method means.

(1)Can someone share scheamtic for unregulated method

(2)Can someone share proper schematic for regulated method.

IN preliminary section on cy8c58LP datasheet figure 2.5 is what kind circuit.(regulated or unregulated)

Please guide as this power section has to be perfect.  I know i sound noob here but power section is confusing part of psoc 5lp

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1 Solution
Len_CONSULTRON
Honored Contributor II

quad,

1.5 inches away ... hmm.  Is the smps in a Faraday cage enclosure?  Ie:  Is the smps assembly have a wire mesh surrounding it?

Q1)

Optimally, it is better to Faraday shield the "offender" (smps) than the one "offended" (your design).  Faraday shields can be simple but it's an added cost everyone wants to avoid.

Given the small distance to your PCB, there are other mitigation techniques but each one will add costs.

In general, the "low-hangiing-fruit" of mitigation will be a 4-layer PCB.  This should allow the most mitigation with the lowest overall cost of BOM components and manufacturing problems.

Suggestion:  You've already prototyped using your PSoC5-kit.  Try to package all your components as close to production-intent in a prototype housing.  See if your design is prone to RE EMI as is.  If it is, try Faraday shielding on the smps.  If it goes away or improves, the smps is a source of the noise.

Knowing if there is potentially a problem or not, design your production-intent PCB with the best layout practices available in the industry.  This may require some research on the internet or a book resource.

Send this layout to a prototype PCB manufacturer for a quick-turn low-cost run of 5 to 10 PCBs.   Assume if there is a noise issue, you may need more than one revision of the design.  It sucks but it is commonly a reality.   This is because EMI issues can be what I call "Science-Voodoo".  The physics of design is exact (hence the Science part) but the environment it operates in is VERY COMPLEX (hence the Voodoo).  Experienced engineers use as much personal experience as well is outside experts as "lessons learned" to start a design.  Even with this as a good head-start, surprises are not uncommon.  Surprises = Opportunities for new lessons learned.

Q2)

Be careful when using different LDOs to supply VDDD and VDDA.  This could cause unnecessary issues.  The reason there is a concern when directly connecting VDDD directly to VDDA is that sometimes the high-speed switching currents to clock logic in the digital domain can be seen as supply transients in the analog domain.

Here's a low-cost suggestion:

Each supply domain is de-coupled with a cap (C_5 and C_6).  These caps MUST BE placed a close to the PSoC pins as physically possible.  There is a 0 ohm resistor is a place-holder for a potential in-line ferrite bead inductor.  As needed, you can replace the 0R with some in-line inductance to minimize VDDD switching influences on VDDA.  If no inductance is needed, a 0 ohm resistor is very low cost.  In this design, it shares 5V for VDDD and VDDA to use only one Vreg.

pastedImage_4.png

Len

Len
"Engineering is an Art. The Art of Compromise."

View solution in original post

23 Replies
prbh_3338016
Contributor

Guru's

need help

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Len_CONSULTRON
Honored Contributor II

quad,

I'm not sure what you are specifically referring to regarding "regulated or unregulated".  Can you be more specific?  Are you referring to the Power supply to the PSoC or the ADC vref voltage?

General Principles

The PSoC can operate over a fairly wide-range of supply voltage.  2.0V to 5.5V.  IT IS ALWAYS BETTER TO HAVE A STABLE, RELIABLE POWER SUPPLY VOLTAGE!

If you're using the PSoC5LP-kit, it's normally powered by USB @ 5V nominal.  In reality it is about 4.7V +/- 10%.  It should be fine for all digital circuits but some care needs to be used for analog circuits.

I have found to get the most stable and reliable ADC readings I use the internal reference source  pastedImage_0.png.  I recommend on the 5LP-kit to set the ADC vref to Internal Bypassed to pins P0.3 or P3.2.  These pins have a 1uF cap on it to better stable the vref signal.  By using the internal voltage source, your ADC readings will be virtually immune from Vdd power supply fluctuations.

Since you are using 20bits for the ADC, it is going to be near to impossible to eliminate jitter in the signal.  There is going to be multiple sources of noise such as thermal, radiated emissions and more.  Therefore, if possible, take multiple readings and average the result.

I hope this helps.

Len

Len
"Engineering is an Art. The Art of Compromise."
prbh_3338016
Contributor

Thanks for your interest and reply.

I am actually need help reagarding power supply section as i mentioned .

there are two modes psoc 5lp operates in regulated and non regulated. i need 20bit performance from adc.

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prbh_3338016
Contributor

you have edited your reply.

I make use of internal 1.024v vref and used digital low pass filter and also have average the readings.Reading is proper but didnt use by-pass cap for internal ref voltage though.  As i need to design pcb now i need inputs for power supply section

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Len_CONSULTRON
Honored Contributor II

quad,

Are you planning on using the 5LP-kit as the base of the design or are you designing a totally new PCB with the PSoC5LP on it?

If you're using the 5LP-kit as the base, then the USB power is all you get unless you remove R20 on the PCBA and supply your own power to J4 pin 2.

Either way, if you supply your own power, REGULATED is ALWAYS BETTER.

You can purchase very low-cost LDO (Low-DropOut) linear regulators that are easy to design.  An LDO is generally better if you're looking for 20-bit performance.  This is because switching power supplies can be prone to emitting radiated EMI that might be seen by the inputs to your ADC design.  This can be a large contributor to the input signal jitter I mentioned earlier.

Len

Len
"Engineering is an Art. The Art of Compromise."
prbh_3338016
Contributor

thanks. a query arised. The circuit should be exactly same as in TRM of psco 5lp ?. I just need to add the two LDO's one for digital and other for analog?.

Also if seen properly the VCCD pin is left floating in the sample application circuit of TRM This pin number is 86. where to connect this pin.

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Len_CONSULTRON
Honored Contributor II

quad,

Are you happy with the ADC performance on your PSoC5LP-kit prototype?

If so, look at the 5LP-Kit schematics.  This will give to a decent hint how to connect all VDDx, VCCx, VDDIOx, VSSa and VSSd connections along with the bypass cap values.

What is the source of your power supply?  A battery (vehicle or  power cell)?  A wall-AC converter to 5V DC?

Next, you need to consider the susceptibility of your analog inputs to radiated (RE) or conducted (CE) EMI.

Here is a general rule:  Make sure you have a very low-impedance path from your GND-referenced input and VSSA pins on the PSoC.  It is better to use differential input mode to improve RE and CE EMI immunity.  It is preferable to use a 4-layer PCB design especially if there is a lot of routing around the PSoC.   Using a 2-layer PCB requires much more care in the layout to prevent break-up of GND path.

I've looked at the PSoC 5LP TRM.  Are you referring to Section 15.2 Block Diagram, Figure 15-1. Power Domain Block Diagram?

Len

Len
"Engineering is an Art. The Art of Compromise."
prbh_3338016
Contributor

Dear Len and Gill,

I am sorry previously i didnt mentioned some point listed below.

I am happy with kit-059  adc results as thermocouple readings are ok. But this is prototype. Everything is designed and tested on psoc5lp kit059. but i want to design the final product now using cy8c5868axi-lp035 psoc Tqfp 100pin.

so In real world pcb is to be designed. client needs psoc circuitary to be driven by the  230AC input smps module giving output of 12volt dc. I am afraid of jitters from smps output.  I am afraid this will lower the 20 bit adc performance..

Thus i was asking help on designing the psoc5lp power input section.

230voltAC smps--->output12volt dc--->need to design psoc input power section---->psoc5Lp cy8c5868axi---->good 20bit adc performance

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Len_CONSULTRON
Honored Contributor II

quad,

A smps is OK if the smps circuit is not on your PCB.  If it is in a "wall-wart" module with a DC output, the physical distance to your PCB will be most likely enough isolation.  If the smps is very close to your PCB, not so much.

If the smps is a regulated DC output at 12V, then here is a simple low-cost circuit to use to output 5V to the PSoC and downstream circuits.

pastedImage_0.png

The Vreg U_1 can be a very low-cost LDO with a fixed 5.0V output.  Note: most SMD LDOs are about 100mA max output.  With proper thermal design, you can use a 1A version (usually a beefier package) if needed.

The bulk caps C_2 and C_3 are for low-frequency mostly load variances.  C_4 (smaller value but high-frequency lower-impedance) is used to filter possible smps-induced high frequency noise from passing through the Vreg.

Len

Len
"Engineering is an Art. The Art of Compromise."
prbh_3338016
Contributor

user_119654 wrote:

quad,

A smps is OK if the smps circuit is not on your PCB.  If it is in a "wall-wart" module with a DC output, the physical distance to your PCB will be most likely enough isolation.  If the smps is very close to your PCB, not so much.

If the smps is a regulated DC output at 12V, then here is a simple low-cost circuit to use to output 5V to the PSoC and downstream circuits.

pastedImage_0.png

The Vreg U_1 can be a very low-cost LDO with a fixed 5.0V output.  Note: most SMD LDOs are about 100mA max output.  With proper thermal design, you can use a 1A version (usually a beefier package) if needed.

The bulk caps C_2 and C_3 are for low-frequency mostly load variances.  C_4 (smaller value but high-frequency lower-impedance) is used to filter possible smps-induced high frequency noise from passing through the Vreg.

Len

Great explanation  Len sir.

Now i am close to designing the pcb . But last few queries.

(1) smps is modular pcb which will be inside cabinet of the product a 1.5 inch away from psoc board. now i need to know what protection circuitry is needed to not to harm the 20 bit adc performance .

(2) As per ap note to acheive analog performance digital supply and analog supply regulator should be different and so the grounds aswell.

Do i need to used two ldos. I am willing to use AMS1117-adj or AMS1117 5v and AMS1117 3.3volt regulators. ALL other components driving higher current will make use of other regulator.  I am thinking that  proper load distribution will keep the thermal heat to minimum as the product will be in plastic cabinet.

This post queries will help many others out there to achieve success. As power section if not designed properly can lead to hidden errors.

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Len_CONSULTRON
Honored Contributor II

quad,

1.5 inches away ... hmm.  Is the smps in a Faraday cage enclosure?  Ie:  Is the smps assembly have a wire mesh surrounding it?

Q1)

Optimally, it is better to Faraday shield the "offender" (smps) than the one "offended" (your design).  Faraday shields can be simple but it's an added cost everyone wants to avoid.

Given the small distance to your PCB, there are other mitigation techniques but each one will add costs.

In general, the "low-hangiing-fruit" of mitigation will be a 4-layer PCB.  This should allow the most mitigation with the lowest overall cost of BOM components and manufacturing problems.

Suggestion:  You've already prototyped using your PSoC5-kit.  Try to package all your components as close to production-intent in a prototype housing.  See if your design is prone to RE EMI as is.  If it is, try Faraday shielding on the smps.  If it goes away or improves, the smps is a source of the noise.

Knowing if there is potentially a problem or not, design your production-intent PCB with the best layout practices available in the industry.  This may require some research on the internet or a book resource.

Send this layout to a prototype PCB manufacturer for a quick-turn low-cost run of 5 to 10 PCBs.   Assume if there is a noise issue, you may need more than one revision of the design.  It sucks but it is commonly a reality.   This is because EMI issues can be what I call "Science-Voodoo".  The physics of design is exact (hence the Science part) but the environment it operates in is VERY COMPLEX (hence the Voodoo).  Experienced engineers use as much personal experience as well is outside experts as "lessons learned" to start a design.  Even with this as a good head-start, surprises are not uncommon.  Surprises = Opportunities for new lessons learned.

Q2)

Be careful when using different LDOs to supply VDDD and VDDA.  This could cause unnecessary issues.  The reason there is a concern when directly connecting VDDD directly to VDDA is that sometimes the high-speed switching currents to clock logic in the digital domain can be seen as supply transients in the analog domain.

Here's a low-cost suggestion:

Each supply domain is de-coupled with a cap (C_5 and C_6).  These caps MUST BE placed a close to the PSoC pins as physically possible.  There is a 0 ohm resistor is a place-holder for a potential in-line ferrite bead inductor.  As needed, you can replace the 0R with some in-line inductance to minimize VDDD switching influences on VDDA.  If no inductance is needed, a 0 ohm resistor is very low cost.  In this design, it shares 5V for VDDD and VDDA to use only one Vreg.

pastedImage_4.png

Len

Len
"Engineering is an Art. The Art of Compromise."

View solution in original post

prbh_3338016
Contributor

Thanks for the reply.

I had already suggested this to the client but now I will make sure to use faraday cage as this is best option.

What if i use two LDO's?.apnote also suggest the same for good analog performance. I think i should separate the analog and digital section. what you suggest.   As I need this thing to be working for demo. Atleast i can try to keep the performance upto the mark . The analog ldo will not add much cost though.

Q2)

Be careful when using different LDOs to supply VDDD and VDDA.  This could cause unnecessary issues.  The reason there is a concern when directly connecting VDDD directly to VDDA is that sometimes the high-speed switching currents to clock logic in the digital domain can be seen as supply transients in the analog domain.

Len

what unnecessary issue sir?  if i use two ldo's.

I think problem may arise if i connect and share vddd to vdda.

Also i am thinking to shield the psoc itself .

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Len_CONSULTRON
Honored Contributor II

quad,

Some of the unnecessary issues are:

  • The Vreg for VDDA is faulted OFF and the CPU (running off VDDD) ASSUMES VDDA is good.  Fix:  Check for VDDA LVD (Low-Voltage Detect) before performing a Analog function.
  • Be careful of analog circuits driven by VDDD power.  There might be a back-feed of current from VDDD especially if VDDA is significantly lower than VDDD or faulted off.
  • Fewer BOM components mean lower MTTF (Mean-Time-To-Failure).
  • A simpler assembly with fewer chances for assembly failure in mass-production.  Also fewer test points.

It's your call.  My normal "go to" decision is try it from the same Vreg and upgrade to a dual-Vreg design if the results aren't good enough.

Suggestion:  If you're design allows it, construct a layout where you can have 'Protect4' design elements.  You can 'Protect4':

  • two Vreg. (Second Vreg optional)
  • One common Vreg with the filtering shown in an earlier post. (Optional installable filter comps)
  • Attachment points for a Faraday shield. (Optional install)

One you get the first revision of the PCB, you can start with the simplest, low-cost cost solution [One Vreg with filtering] (this always makes the customer happy).

You can experiment by adding the second Vreg.  Do you see improvements?

If needed, you can add the Faraday shield.  Improvements?

Once you have a solid solution, you can either commit the design with that revision of PCB or go through an layout to remove unneeded 'Protect4' components.

Len

Len
"Engineering is an Art. The Art of Compromise."
prbh_3338016
Contributor

Thanks a lot Len and Gill,

I appreciate the knowledge share to me. I will design the circuitry, develop the pcb and the post the circuits following this topic. So that many new users can take a knowledgeable inputs and learn to built power section.

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JOLO_264146
New Contributor II

Hi,

as reference fyi. I use this design as core module (for P3 and P5LP). I'have one similar for P1 (with connectors in the same position and with same signals) and I'm finishing other for P62 and P63 (although these last ones are in stand by. I prefer to use P3/P5LP )

prbh_3338016
Contributor

p1 psoc1

p3and p5 psoc 3 psoc5lp

p6 psoc 6 

I got it.

Refrence design is good.  It would be helpful. Thanks a lot..

I am not greedy   but can you share board files. which software is this used for schematic / pcb design

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JOLO_264146
New Contributor II

Hi,

I use a "old" version of Orcad (10).

Attached the files

Regards

Gil

prbh_3338016
Contributor

thank you gil,

i have finished the design of pcb yesterday. But the shcematic u shared will help to cross verify . thanks a lot

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JOLO_264146
New Contributor II

Hi,

the P5LP (and P3) has several voltage domains (see detailed explication in DS - https://www.cypress.com/documentation/datasheets/psoc-5lp-cy8c58lp-family-datasheet-programmable-sys... , page 12)

I assume that you are going to make a "simple" PCB using, if possible, only one voltage

I assume that everything about how to deal with high resolution ADC and small signals is observed (trace of PCB, filtering, components used, etc,etc) 

I don't know what's your voltage in your circuit. As Len said, for high resolution ADC is always better to use LDO (no switching), with its filtering / decoupling.

On the side of P5LP, it's better to use those pins with "quasi" direct connection to ADC (internal routing in P5LP is intended to minimize the possible crosstalk noise between analog, digital, clocks, etc See AN58304 and others)

You can use only one voltage for all power supply pins: VDDA (must be the highest), VDDD, VDDIO(0,1,2,3).

PIns VCCA and VCCD are generated, so, you need only decoupling capacitors (see fig 2-5 in DS).

In case you have to connect signals with other voltage levels (i.e. your main power is 5V but you have devices powered at 3.3V and 1.8V), you can connect VDDIOx at the voltage of your device (you can have until 4 different domains) so, you don't need voltage translators. If it's not your case, connect VDDIOx to VDDA

Follow the recommendation if you're not going to use battery (VBAT) and / or you don't need boost the voltage (i.e in the case you are usin solar panel)

A recommendation (my experience): for high resolution, use external Vref (1.024 as max. voltage). I use LM4140 with very good results.

B.R.

Gil

prbh_3338016
Contributor

I assume that you are going to make a "simple" PCB using, if possible, only one voltage

I assume that everything about how to deal with high resolution ADC and small signals is observed (trace of PCB, filtering, components used, etc,etc) 

I don't know what's your voltage in your circuit. As Len said, for high resolution ADC is always better to use LDO (no switching), with its filtering / decoupling.

Dear Gill,

Please tell me single LDO will do the work as I have cost constraints too. I was willing to use ams1117 for digital and  LM317adj for analog. I other peripherals ic like max7291 seven segment ,rtc, eeprom,max485,sd card power, etc will be power by other Third LDO regulators. 

Or can your suggest low cost LDO and share or suggest design which has been proven by you.

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prbh_3338016
Contributor

On the side of P5LP, it's better to use those pins with "quasi" direct connection to ADC (internal routing in P5LP is intended to minimize the possible crosstalk noise between analog, digital, clocks, etc See AN58304 and others)

You can use only one voltage for all power supply pins: VDDA (must be the highest), VDDD, VDDIO(0,1,2,3).

PIns VCCA and VCCD are generated, so, you need only decoupling capacitors (see fig 2-5 in DS).

In case you have to connect signals with other voltage levels (i.e. your main power is 5V but you have devices powered at 3.3V and 1.8V), you can connect VDDIOx at the voltage of your device (you can have until 4 different domains) so, you don't need voltage translators. If it's not your case, connect VDDIOx to VDDA

What is " Quasi" direct connection to adc.

PIns VCCA and VCCD ALL the pins on psoc should be bypassed using 1uf or 0.1Uf?

other pheripherals with 3.3v requirements have been taken care using 3.3volt and voltage level shifters

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JOLO_264146
New Contributor II

Hi quad,

read AN58304 carefully.. You have the info about what pins (and ports) are better to use for analog.

VCCA and VCCD: it's 1uF. Follow the rules described in DS. (there is also a example of PCB how to distribute the capacitors).

why to use voltage level shifters when you can connect them to P5LP directly? You only need to apply 3.3V to the VDIOxx that cover the port pins used.

Imagine that you have a AND gate (3 inputs), with inputs at 5V level but you need the output connected to 3.3V level. A solution: input: P5[0..2] and VDIO01 = 5V; Output: P6[7] and VDIO02 = 3.3V. Done.

B.R

Gil

prbh_3338016
Contributor

user_62908756 wrote:

Hi quad,

read AN58304 carefully.. You have the info about what pins (and ports) are better to use for analog.

VCCA and VCCD: it's 1uF. Follow the rules described in DS. (there is also a example of PCB how to distribute the capacitors).

why to use voltage level shifters when you can connect them to P5LP directly? You only need to apply 3.3V to the VDIOxx that cover the port pins used.

Imagine that you have a AND gate (3 inputs), with inputs at 5V level but you need the output connected to 3.3V level. A solution: input: P5[0..2] and VDIO01 = 5V; Output: P6[7] and VDIO02 = 3.3V. Done.

B.R

Gil

Gil ,

sir excellent explanation. This cleared all my doubts in one shot. I can feel how powerful and flexible is psoc.

I will not be using 3.3volt reg now. I am now confident to go ahead with the design.

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