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Hi,
How can I monitor hard fault in PSoC 5LP.
What would happen if I’m not create a special ISR for Hard fault?
Is the software continue to run when hard fault is occur?
Thanks
Shmuel
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Hi,
May be this is not the elegant approach, and I have not been able to test it though,
In Genereated_Source/PSoC5/cy_boot/Cm3Start.c, there is following block
========================
/*******************************************************************************
*
* Default Rom Interrupt Vector table.
*
*******************************************************************************/
#if defined(__ARMCC_VERSION)
/* Suppress diagnostic message 1296-D: extended constant initialiser used */
#pragma diag_suppress 1296
#endif /* defined(__ARMCC_VERSION) */
#if defined (__ICCARM__)
#pragma location=".romvectors"
const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] =
#else
CY_SECTION(".romvectors")
const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
#endif /* defined (__ICCARM__) */
{
INITIAL_STACK_POINTER, /* Initial stack pointer 0 */
#if defined (__ICCARM__) /* Reset handler 1 */
__iar_program_start,
#else
(cyisraddress)&Reset,
#endif /* defined (__ICCARM__) */
&IntDefaultHandler, /* NMI handler 2 */
&IntDefaultHandler, /* Hard fault handler 3 */
};
========================
If you define "MyHardFaultHandler" somewhere in your project as below
==============
CyISR(MyHardFaultHandler)
{
/* do something for the Hard Fault Exception */
}
==============
changing the line
> &IntDefaultHandler, /* Hard fault handler 3 */
to
< &MyHardFaultHandler, /* Hard fault handler 3 */
may take care of what you want to do.
Again, please note that I have not been able to test it,
so please proceed at your own risk.
moto
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There is a defaulted dead loop when an unhandled interrupt occurs. You may (or need to) install your own handlers. Have a look at the vector table (excerpt from ARM: "Cortex M0 Devices Generic User Guide").
Bob
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Hi,
May be this is not the elegant approach, and I have not been able to test it though,
In Genereated_Source/PSoC5/cy_boot/Cm3Start.c, there is following block
========================
/*******************************************************************************
*
* Default Rom Interrupt Vector table.
*
*******************************************************************************/
#if defined(__ARMCC_VERSION)
/* Suppress diagnostic message 1296-D: extended constant initialiser used */
#pragma diag_suppress 1296
#endif /* defined(__ARMCC_VERSION) */
#if defined (__ICCARM__)
#pragma location=".romvectors"
const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] =
#else
CY_SECTION(".romvectors")
const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
#endif /* defined (__ICCARM__) */
{
INITIAL_STACK_POINTER, /* Initial stack pointer 0 */
#if defined (__ICCARM__) /* Reset handler 1 */
__iar_program_start,
#else
(cyisraddress)&Reset,
#endif /* defined (__ICCARM__) */
&IntDefaultHandler, /* NMI handler 2 */
&IntDefaultHandler, /* Hard fault handler 3 */
};
========================
If you define "MyHardFaultHandler" somewhere in your project as below
==============
CyISR(MyHardFaultHandler)
{
/* do something for the Hard Fault Exception */
}
==============
changing the line
> &IntDefaultHandler, /* Hard fault handler 3 */
to
< &MyHardFaultHandler, /* Hard fault handler 3 */
may take care of what you want to do.
Again, please note that I have not been able to test it,
so please proceed at your own risk.
moto
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In the initialize_psoc() function called prior to the main() function, the vector table is initialized on a RAM area.
/* Set Ram interrupt vectors to default functions. */
for (i = 0u; i < CY_NUM_VECTORS; i++)
{
#if defined (__ICCARM__)
CyRamVectors = (i < CY_NUM_ROM_VECTORS) ? __vector_table.__fun : &IntDefaultHandler;
#else
CyRamVectors = (i < CY_NUM_ROM_VECTORS) ? RomVectors : &IntDefaultHandler;
#endif /* defined (__ICCARM__) */
}
So, it is enough to modify the vector table on the RAM like
CY_ISR(hardFaultIsr) {
}
:
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
ramVectorTable[CY_INT_HARD_FAULT_IRQN] = hardFaultIsr;
}
Please note that I didn't confirm if this works on silicon.
Regards,
Noriaki
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Dear Noriaki-san,
May be this is a corner case, but if there is a hardware fault at POR,
your method may not work, right?
Best Regards,
22-Jul-2019
Motoo Tanaka