PSoC™ 5, 3 & 1 Forum Discussions
Hi,
I am trying to interface i2c EEPROM and RTC (24LC512 from Microchip and DS1307) CY8C28452,
i am using I2Cm module and configure P2_7 as SDA and P2_6 as SCL. also configure pin as OPEN DRAIN LOW and pull up the pins with 4K7 E resistor.
i use the source code provided in data sheet. but it not works. i check with CRO their is no pulsing on P2_7 as SDA and P2_6 as SCL. then i change pull up to 2k2 but still same thing.also i try with only RTC on board but no op my disply show me error.
i used system clk 24Mhz and CPU clk system clk / 2.
please help me
Show LessHi
Please can you let me know the FIT and MTBF information of CY8C9560A-24AXI IO expander IC
Regards
Abishek V
I am using a PSOC 5 (CY8CKIT-059) as a SPI slave in a project. I am trying put a status byte in the slave SPI tx buffer to serve as the default data read by the master when there is no data to transmit from the slave. A ready byte when the slave is not processing, a busy byte when it is (or actual data from the slave).
The psoc's rx buffer is handled via dma. When the dma irq triggers for the single command byte, it clears the tx buffer (hardware), and places the busy byte in the tx buffer while it figures out what to do with the command received in the main loop. When it done executing the command, it clears the tx fifo once again and places the ready byte in the tx buffer. The problem I am running into is that at higher spi speeds (200khz in this case), the ready byte does not appear to be placed in the tx fifo. Instead, the busy byte is always returned. At lower speeds, it works as expected. I have included a bare-bones project showing the problem. Single bytes come in from the master at approx a 1 sec interval so there should not be a timing problem replacing the busy byte with the ready byte in the tx buffer. Nevertheless, the response received by the master will change based on the bus speed (at speeds around 190000 and higher, the slave will always respond with busy). Any idea what is going on here?
#define PSPI_READY 0xAD
#define PSPI_BUSY 0xAA
static uint8_t _PSPI_DMA_TD = 0x00;
static uint8_t _PSPI_DMA_Channel = 0x00;
volatile uint16 _PSPICMDFlags = 0x00;
volatile uint8_t _PSPICurCMD = 0x00;
uint8_t _PSPIInputBuffer[PSPI_BUF_SIZE] = {0};
volatile static uint32_t _PSPIRecvCnt = 0;
void Init_PSPIDMA(void) {
// we are going to grab 1 byte from the SPI at a time
_PSPI_DMA_Channel = PSPI_DMA_DmaInitialize(1,1, HI16((uint32)PSPI_RXDATA_PTR), HI16((uint32)(&_PSPIInputBuffer[0])) );
/* Allocate TD - _PSPI_DMA_TD */
_PSPI_DMA_TD = CyDmaTdAllocate();
/* Set the source of TD_rx as SPIS_RXDATA_PTR Address and the destination SPI slave Rx Buffer */
CyDmaTdSetAddress(_PSPI_DMA_TD, LO16(((uint32)PSPI_RXDATA_PTR)), LO16(((uint32)&_PSPIInputBuffer[0])));
// Set _PSPI_DMA_TD as the initial TD associated with _PSPI_DMA_Channdel
CyDmaChSetInitialTd(_PSPI_DMA_Channel, _PSPI_DMA_TD);
PSPI_RX_DMA_Done_ISR_Start();
}
// set up DMA to transfer burstCnt bursts of 1 byte from the PSPI rx
// our DMA irq will trigger letting us know when the data is available
void Set_PSPICmdDMATransfer(uint16_t burstCnt, uint8_t respByte, uint16_t status) {
// assuming the SPI device will echo the last byte in the tx fifo, we will add a busy
// byte so the master will know when we are done processing the last command
// this will happen when we change the tx fifo byte to PSPI_READY
//PSPI_ClearFIFO();
PSPI_ClearTxBuffer();
PSPI_WriteByte(respByte);
_PSPICMDFlags = status;
CyDmaTdSetConfiguration(_PSPI_DMA_TD, burstCnt, DMA_DISABLE_TD, TD_INC_DST_ADR | PSPI_DMA__TD_TERMOUT_EN);
CyDmaChEnable(_PSPI_DMA_Channel, 1);
}
void PSPI_RX_DMA_Done_ISR_Interrupt_InterruptCallback(void) {
_PSPIRecvCnt = 0;
PSPI_ClearTxBuffer();
PSPI_WriteByte(PSPI_BUSY);
// This DMA interrupt will trigger in three cases
// In the first, the DMA transfer of a PSPI command byte has finished
if (_PSPICMDFlags == PSPI_IDLE) {
_PSPICMDFlags = PSPI_CMD_READY;
_PSPICurCMD = _PSPIInputBuffer[0];
// setting up dma here appears results in the ready byte being in the tx buffer
// Set_PSPICmdDMATransfer(1, PSPI_READY, PSPI_IDLE);
}
}
void Init_System(void) {
// turn on the PSPI connection
PSPI_Start();
// start the irq that handles possible lockups
// PSPI_SS_IRQ_Start();
// prepare the PSPI DMA for incoming PSPI data
Init_PSPIDMA();
// and set up the dma transfer for the command byte
Set_PSPICmdDMATransfer(1, PSPI_READY, PSPI_IDLE);
}
int main() {
CyGlobalIntEnable; /* Enable global interrupts. */
Init_System();
//Handle_LCDDemo();
while(true) {
// we received a command byte so figure out what we need to to do
if (_PSPICMDFlags == PSPI_CMD_READY) {
//Handle_PSPICommand();
// setting up dma here does not place ready byte into tx buffer
Set_PSPICmdDMATransfer(1, PSPI_READY, PSPI_IDLE);
}
}
}
Show Less
How can I read the unique id from PSoC 5LP devices within ppcli?
Refering to PSoC 5LP Registers TRM and according to code generated (CyLib.c and cydevice_trm.h the unique is stored at addresses like 0x4900 010x (with exception of CYREG_MLOGIC_REV_ID referring to 0x400046ec).
How can I retrieve these values for production purposes before flashing user code (i.e. without executing user code)?
I tried things like PSoC3_ReadRow 0x4900 0x0n 0x00 (n = 0..F) but the given results do not seem to contain right values.
Is there a function for reading data from random (existing) addresses in address space?
Show LessWhen we made Port 1 Hi Z Analog, we can no longer program the PSoC3 with our host chip, but can still program with the MiniProg3. Our host chip uses active drive up/down when writing and driving XRES, and a pullup with receiving.
We found the problem - in PSoC Creator 4.3, when we set the pin to Hi Z Analog, it of course made the all of Port 1 Hi Z Analog. There was a side effect - in the Design Wide Resources > System section, it changed Programming\Debugging Debug Select to GPIO, which knocked out our ability to program from our host chip. We then changed it back to SWD, we could then program from our host chip.
On a side note, even while Programming\Debugging Debug Select was set to GPIO, the MiniProg3 could still program the chip - can you tell us how that can happen?
We have a few boards at remote locations with out MiniProgs, and we'd like to be able to recover those chips with the host processor only.
Show LessCypress PSoC CY8C3246LTI-162 - date code (611327)
When Cypress goes into a Sleep mode for "good" boards the current draw drops to 50uA on boards with the above date code the board draws ~24mA on the "bad" units.
Do you know any changes that may have been made on the Cypress side recently?
These products haven't had a FW or HW ECO since 2016. The boards were assembled wk17 of 2021.
Show LessHi All,
I am using CY8C5467AXI-LP108 chip.
I am having difficulty to compile these analog pins:
P4_3/PIN81
P15_4/PIN93
P15_5/PIN94
Receiving this error message:
"apr.M0003:Unable to find a solution for the analog routing."
I have looked up in the datasheet and didnt see any problem using these pins as analog pins.
This is my schema, all the other analog pins are good and fully functional:
Thanks,
Roy Roif
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Hi,
I am trying to configure multiple pins connected to interrupts but I receive an error [see attached pictures].
Thanks,
Roy Roif
Show Less
Hi all,
I am currently working on a project that requires the logging of some events. This requires more capacity than that provided by the EEPROM so I am now considering using the rest of the flash space available (256k in total).
My only concern with doing this is that I would need to know which is the last row that contains my code as I do not wish to overwrite any of this of course.
I have been looking around and do not seem to be able to find any information on this. Would anyone know how to tell which rows are safe to write?
My device also uses a Bootloader, which only leaves me with the space between the last application row and the first metadata row.
Show Less