PSoC™ 5, 3 & 1 Forum Discussions

Hello there! 🙂

Just simple question.

On the Block Diagram may I left my nickname or it should be without any information of the designer?

I already submit the block diagram, so you can see what I mean.

Kind Regards,

electronix79

Kiku and Graa et al.

Back 5 years ago the packaging problem was simple, because your devices only came in a couple of packages. But now... Holy crow.

The problem is that now we need to wade through umpteen data sheets trying to match a package to an app.  Not fun.

I know that QFN is your basic package, but it would be a huge help to have a document -- a table perhaps -- that shows which offerings come in which packages.  This needs to cover PSOC1, 3, and 5.  My ideal doc would be a table showing device sorted by pin count by package type.  So I could quickly see which PSOC 3 devices come in a 48 pin SSOP and which PSOC 5 devices come in 48 pin QFNs, etc.

Please put this on the doc list.

My question is quite straight forward.

It is possible to program PSoC 1 devices with PSoC Creator?

Why we have two diferent tools: PSoC Designer for PSoC 1 and

PSoC Creator for PsOC 3 and 5?

Thanks.

All, I am trying to see the EOC output from the Cypress Example ADC to LCD. I have tied the EOC output to a digital pin so that I can check timing on an O-Scope. All I am seeing is a logic HI. I have attached a screen shot of the CYSCH file.

Any ideas.

Keith

I'm using a PSoC3 dev kit as a SPI master talking to my project board.  To get the SPI bus synced between them I hold the reset on the dev board then reset my project board then release reset on the dev board and they are in sync.  In the future the dev board will be a main controller board and this will need to work on power up.

I would like my project board to sync with the dev board automatically when it's reset and possibly in between packets at runtime to correct bit errors.  My question is does the SS re-sync the slave SPI?  Doesn't seem to.  Can the SS be connected to the Slave Reset signal to reset/resync it between packets?  If not is there another way to do thi?.  I also tried resetting the slave using a timer tc that would expire if the SPI master CLK was inactive (during reset). 

Another thing, if the reset signal is used on the Slave SPI component does the Start(); function need to be called after every reset?

All, I am needing to Mux the input data into an ADC. For starters, I would like to bring the MUX pins to the outside world. How do I use the BUS to 2 external digital pins? How is it done schematicaly?

Keith

Question: When setting up the Conversion Rate on the DeltaSigma block, is that rate driven by interrupts? So if I sample at 100Ksps (10us), is the interrupt called every 10us to take a sample, or is the timming derived some place else? Where/which interrupt is called to perform the start-conversion?

Keith

All,

I am using the CY8CKIT-001 development kit working on a modified ADC_DMA_Memory_16Bit code. I have my samples set to 8000 and the ADC rate set to 4000, which should be 2 secs worth of recording.

It doesn't record for 2 sec, but.... the actual point I am addressing here, is.... I have an LED indicator that tells me the program is ready for recording. It works as planned when I either reprogram the board, or remove power and re-apply power... but when I hit the "Reset" switch on the eval board, I never get an indicator that the program has reset and is now ready for recording.

Any ideas??

Keith