PSoC™ 5, 3 & 1 Forum Discussions

These are the 3 third party programming support Cypress qualified for PSoC 3 so far:

RPM;

Elnec;

System General

To scan each CapSense element, the scanning time can be divided into three time periods pre-scan, post
scan and hardware time for scanning. The hardware time for scanning does not require CPU and the CPU can be
shut off during this time to save power. After the hardware scanning of button an interrupt will be generated and the
CPU wakes up on this interrupt.

Call the API to scan all the sensors “CapSense_ScanEnabledWidgets()”, it will set the CapSense
parameters for the button, starts the hardware scan and returns the main function. Next line of code in the main loop
is API “CyPmAltAct()”,which puts the device into alternative active mode. Alternative active mode by default
is configured such that it will have all the blocks running/disabled same as in the active state but CPU is shut down.
When the hardware finishes the scanning a button it generates an interrupt and the CPU wakes up and it starts
executing the ISR code which is post scan time.

This is one of the many benefits of PSoC 3 CapSense that is based on the hardware universal digital block implementation.  Please stay tuned as we are exploring more...

Here are the 11 marketing part nubmers that you can order right now:

To see what end equipments you can design with PSoC 3 & 5, please check out our new application websites. For example:

Blood Glucose meter: http://www.cypress.com/?rID=43661

LED Projector: http://www.cypress.com/?rID=47831

The system block diagrams here show what can PSoC integrates and what are the unique PSoC Builidng blocks that MCUs can not implment.

These content are all gathered at www.cypress.com/go/psoc3 page, under the PSoC 3 & 5 Solution section.

Hi All,

Online training material is available at Cypress website at the following link:

http://www.cypress.com/?app=search&searchType=advanced&keyword=&rtID=134&id=0&applicationID=0&l=0

The matrial includes:

    
• PLD Based Verilog Components
    
• Introduction to Component API Generation
    
• Component Parameters
    
• Schematic Components
    
• Intro to Datapath Components
    
• Datapath API Generation
    
• Multi-Byte Datapath Components
    
• Datapath FIFOs
    
• Datapath Computation
    
• Introduction to Digital Peripherals
    
• Introduction to Analog Peripherals
    
• Introduction to System Resources
    
• Introduction to the Architecture and Design Flow
    
• Introduction to CapSense Touch Sensing
    
• Introduction to Architecture and Design
   

Regards,

dasg