PSoC™ 5, 3 & 1 Forum Discussions
I looked at My Account - My Designs web page, and it seems the page is stuck in Phase 1. Submission button is grayed out, status of the project is "In Process"... I have the dev kit and my design is showing on the Cypress website for voting in Phase 2 ("Engine Monitor"). How to submit materials for Phase 2 ? Thanks!
Show LessAll,
background: you can only use PSoC Creator together with a PSoC 3 or PSoC 5 in mind. It is possible to evaluate the user interface of Creator without hardware but you will get stuck sooner or later.
On the other hand, when you are using PSoC 5 you will use Creator by definition because it is the only tool to configure the hardware of PSoC 5
Because these subjects, PSoC Creator and PSoC 5 are so closely related, we are discussing to merge the content of both forums and call it a PSoC 5 -- Hardware -- Software -- DevKits forum
You feedback is greatly appreciated and if we get a number of votes, it will have a strong impact on the decision.
Please post your opinion in this thread.
Cheers, Robert
possible answers could be:
1. Great, we can see all related topics
2. Please don't do this, I would like to see these topics separated
3. Either one is fine with me
4. Other: ________________________
Hi, for my design, I'm trying to use the cool slick PrISM component to add 1 bit of dither to a DAC, so I need to put in DAC bus mode. However, when I do so, I get these errors (one per input)
Multiple signals found between VIDACs on data input 0
I'm using two other DAC's which I tried hooking up to the same bus, but I still get it. I'm also using the CapSense_CSD component, which looks like it also uses some DAC's.
So, is there a way to do this somehow?
Thanks for any help!
-Michael
Show LessHello,
My application has a stream of digital values being captured by a FIFO (http://www.cypress.com/?rID=46730). The number of data points sent by my target is 25,344 bytes. I have been able to estabilish a 2-D array in memory of the PSoC 5 device that works.
I am concerned that the DMA might not be able to directly transfer such a large chunk of data. I understand that it has some kind of counter limit?
Does anyone have any suggestions on how to go about this?
Thanks,
DiodeDan
Show LessHi, I'm just starting to think about the video now, and was wondering if there were any guidelines? E.g. about how long, whether it should focus on the development process or the final result, whether we can get outside help with producing it, and whether Matt Damon would be available to play me, since I'm not very photogenic.
Show LessI wanted to interface an SDCARD to my PSOC1 using psoc DESIGNER/Express. And also need to format the sdcard using FAT.
I have worked on I2C with psoc. But how could I interface an SDcard with the user modules?
How could I do that?? Please help me out...
Thanks in advance..
Siv Show Less
Want to know if PSoC meet the Directive 2002/95/EC (RoHS) requirement?
On the web MPN page, look under “Technical Documentation”. For examole
http://www.cypress.com/?mpn=CY8C3244AXI-146 #TechnicalDocuments
This PMDD called out that we meet the Directive 2002/95/EC (RoHS) requirement, and the Substanced/Compounds weight by mg.
In Capsense_CSD, if the debounce is set to say 5 then it means the finger has to be present on the button for so many number of scans. In this case, for five scans the finger has to be on the button. The debounce feature removes the high amplitude high frequency noise.
But when the CapSense is used in the applications, where the main loop is long, the response time of Capsense button may be very poor if the debounce is set to high number. CapSense buttons will be scanned in continuous loop. If the loop is long and the debounce is high like 5, then this long loop should be executed 5 times for the button to be detected as ON. This gives very slow response.
Solutions to avoid this:
1) Debounce value: Do not set this as high number or dont leave it as default value which is 5. If the loop is long then already the interval between scan is long so high debounce number is not needed. Use the debounce value of 2.
2) Do multiple scans in the same loop: Inside the long loop, scan the CapSense buttons twice or more. Decide your debounce time that is how time you want your button to be active to be detected as ON. This depends on the noise freqency in the system. Then do the multiple scannings so that scannings are done to cover the required debounce time.
Show LessOne of the most frequently encountered probelms while writing a C code for an application is that you may run out of code space, RAM space. PSoC 3 has relatively smaller SRAM (8 KB), Flash (64 KB) compared to PSoC 5 devices. Depending on the application you may typically end up needing to,
1.)Optimize SRAM memory utilization
2.)Optimizing Code space
3.)Reducing Code execution time for a code snippet or an Interrupt routine
The 8051 CPU has some very simple yet powerful features for solving above three scenarios. Refer the application note
<a href="http://www.cypress.com/?rID=40986">AN60630 - Optimizing 8051 Code in PSoC® 3 </a>. It explores the 8051 architecture with regards to above points and also explains how Keil compiler supports these features.
The Keil compiler help manual that comes with Creator is another excellent source of reference.
As an example, 1-bit flag variables that can either be only '1' or '0' can be declared as "sbit" rather than a byte.
Any other interesting things you found, feel free to post here.
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