PSoC™ 5, 3 & 1 Forum Discussions
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Hi everybody,
I have an issue, I haven't succeeded to solve it during my working day. ( i'm french)
I attend a sandwich course and for my project I'm working on a Cypress CY38C3246 PVI 122 ( psoc 3).
I can program it without problem With a miniprog3 .
But, because there is a "but", once my Cypress is turned off during a few seconds an issue gets happened.
Though my board is supplied, I must shortcircuit Xres with Vcc to start my cypress.
In situation:
I have connected a LED to show me that my board works.
I supply my board and the light of the LED is very weak and fix. It should blink because I have coded that.
When I shortcircuit xres on Vcc manualy, the LED blinks, it is the evidence that the Cypress works.
Does Someone have an idea?
Thanks in advance.
Antoine G.
I need some help determining the best way to interface the PSoC 3 with and SPI capable ADC. The timing of the ADC sampling must be controlled by the SPI Master (PSoC). That is, the rate at which the master request samples determines the ADC sampling rate. Once a convert command is received by the ADC the result is sent back two CS/SS pulses later.
What is the best way to allow the PSoC to control the ADC sampling timing via the SPI interface? Should I setup a timer to execute an ISR to request data, wait for the data, then send data to buffer? I will need the ADC to take 3000 samples at a rate between 40-60 ksps total. Thus at 60 ksps I would need to send "convert" commands every 1/60ksps = 16.6us. Will there be enough time to send the request, wait for the data, and then DMA it to a buffer?
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Below is a sample of info from the datasheet. I’ve also attached part of the datasheet.
The RHD2000 ADC samples the selected analog signal on the falling edge of CS. The CS line must be pulsed high between every 16-bit data transfer, even when the command word does not request an analog-to-digital conversion. The RHD2000 samples MOSI on the rising edge of SCLK. The master should sample MISO on the rising edge of SCLK. (The master device SPI interface should be configured with SPI options CPOL=0 and CPHA=0.)
After receiving a CONVERT(C) command from the master, the on-chip ADC samples channel “C” on the falling edge of the next CS pulse. The analog-to-digital conversion is performed during the next 16 SCLK cycles, and the result is relayed to the master over the MISO line during the following 16 SCLK cycles (two total commands later).
The RHD2000 uses a pipelined communication protocol; each command sent over the MOSI line generates a 16-bit result that is transmitted over the MISO line two commands later. Communication with the chip is illustrated in the following example diagram:
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Hi,
I am using a filter in PSOC 5, but I am unable to run/build it (i am not using a DMA).
the console says 'undefined reference to `Filter_Write24''
Filter_1_Start();
Filter_Write24(Filter_CHANNEL_A,ADC_sampleValue);
where ADC_sampleValue is a 32 bit uint, and Filter_CHANNEL_A is a uint8 type(how to set this?, ive only declared the variable as a uint8 type), and i have included the following header files:
#include <device.h>
#include "stdio.h"
#include "stdlib.h"
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When non synchronous signals or signals which are not actual clocks are routed as datapath clock, the synthesizer would throw an error telling that, it has to get through the clk enable block to be routed appropriately. What precisely needs to be done is the following,
There is an instance in which we can make the sync mode false and put in that clock signal as an input and take the asynchronous clock as output. That is precisely done below.
Now, we have to wire the a_clk to the datapath.
The synthesizer would yet throw a warning telling us that an asyncronous path exist. We can ignore that warning, because that is what we want:-).
cy_psoc5_udb_clock_enable_v1_0
#(.sync_mode(`FALSE))
PrcClkEn
(
.clock_in(clk),
.enable(1'b1),
.clock_out(a_clk)
);
Regards, Rahul Ram
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When non synchronous signals or signals which are not actual clocks are routed as datapath clock, the synthesizer would throw an error telling that, it has to get through the clk enable block to be routed appropriately. What precisely needs to be done is the following,
There is an instance in which we can make the sync mode false and put in that clock signal as an input and take the asynchronous clock as output. That is precisely done below.
Now, we have to wire the a_clk to the datapath.
The synthesizer would yet throw a warning telling us that an asyncronous path exist. We can ignore that warning, because that is what we want:-).
cy_psoc3_udb_clock_enable_v1_0
#(.sync_mode(`FALSE))
PrcClkEn
(
.clock_in(clk),
.enable(1'b1),
.clock_out(a_clk)
);
Regards, Rahul Ram
Show LessHi, i have a problem with a opamp:
when i don't starting the amp with "opam_start();" in my initialization function there's no problem and it works fine,
but if i do including the "opam_start();" the amp don't works. Which components do i have to start explicit with..._start() and which starts automatically?
Thank you
Im using the Creator 2.1 Pack 4.
Show Less最近在使用cyrf6936,不过在使用的过程中遇到了一些问题。
数据手册上说设定RX GO后,在其未清零前就不能重定设定,我不知道如果重新设定了会出什么问题?
还有那比如我开始对RX_CTRL_ADR写入0X93,当出现中断后(已收到>8个数据时),我能够再不影响接
收时对RX_CTRL_ADR重新写入0X83吗?我是个中国朋友,希望有人能看懂, 为我解答。Thank you!!
Show LessHi to all,
Can anybody tell me what are the necessary modifications to implement pulse oximeter on psoc 3
CY8C3866XAI-040ES2. Here i am attaching the minimal of the oximeter which was done on psoc 1 an example project i got .
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