PSoC™ 5, 3 & 1 Forum Discussions
hi everyone, i have this error on both my desktop and laptop. Unable to open the file for reading. Could not find a part of the path 'C:\Users\sebas\OneDrive\Documents\PSoC Creator\4.4\Downloads ( 4.4).cylib\cy_boot_v6_10\PSoC5\API\cm3gcc.ld'.
this is a fresh install with a new project. i did have psoc before but somehow the programmer got lost so i needed to reinstall it. and now i have this error.
i also needed to reinstall windows on my laptop becouse some how psoc installer was not able to install the updatemaneager.
Show LessHi,
PSoC5 as a versatile MCU is in many ways better than stripped down PSoC6 which focus has gone to IoT/wearable battery powered devices. However there are still many "wired" devices in industry of modern smart sensors, so I wonder if we can collectively gather and vote for requirements for the next generation "PSoC5" sensor controller.
Some starting points from my mind and an amount of psoc projects created so far for the industry:
- m3 to be replaced with psoc6 core logic (m4 + m0 + crypto), and psoc5 has nice 105 oC rated while PSoC6 is still only 85 oC,
- technology shift for lower power, and bring in more RAM, in banks so that DMAs can independently (in parallel) work with different banks without stalling the CPUs; and CPUs between themselves; having m0+ as a comm controller in mind, and m4 as data post-processing controller
- DMA merge best of psoc5 and psoc6
- increase of freq to 200 MHz, adopt GPIO speed from psoc6, but with synchronizers at I/O cells
- Two Delta Sigma, with improved 24-bit resolution @ 100 kSa/s, as many applications require parallel sampling of two values, missing saturation detector and post-sinc correction filter for low-latency; for WB and half-banding filters DFB is/can be used. ADS127L11 is an example of good (lower cost) A/D and the new L21.
- Bring SARs from PSoC4/PSoC6 which bring some post-processing
- Two DFB, existing DFB lacks some more memory to perform computation on larger sets as for FFT
- 100 Mbps LAN / TSN / SPE
- D/A improve resolution to 16-bit, with UDB direct connection for additional modulation/dithering
- UDB FIFO increase to at least 16-bytes, 4 bytes at higher speeds faces latency issues
- UDB 24/32-bit direct access, also on F0+F1 combined registers
- switching pump replace with a "fly-back" controller and open-drain higher voltage fet so it can run in SEPIC mode with ultra low-start-up bias current, then direct connection to <60 V is easily implemented
- LVDS receiver - it is almost there with voltage reference, it's just missing a differential comparator between the two paired SIO pins
- CAN FD
- crystal -> VCXO (internal 16-bit D/A can be used for precise freq control), needed for low-jitter synchronous sampling, i.e. very good low-cost chip CDCE913
Applications:
- ratio-metric measurements, as strain-gauges, thermocouples with CJC, displacement sensors (AC frequency carrier)
- power measurements, and power analysis, voltage, current
- ...
I'm trying to make an address decoder for an 8-bit bus. The Verilog code is extremely simple:
module Decoder (
output IRQ,
inout [7:0] Data,
input [7:0] Address,
input IE,
input RD
);
wire reading = (Address == 8'h40) & !IE & !RD;
assign Data = reading ? 8'h5a : 8'hff;
assign IRQ = 0;
endmodule
This compiles. However, if I change that last line to:
assign IRQ = reading;
...then it fails to compile, with the following errors:
Error: plm.M0046: E2557: Found invalid term <main_0> in eqn_main pterm equation <!main_0> for instance <Net_2281_7>.
Warning: plm.M0029: Ignoring undriven net "\Decoder_1:reading\". (App=cydsfit)
Error: fit.M0050: The fitter aborted due to errors, please address all errors and rebuild. (App=cydsfit)
These look like they're coming from deep inside the Verilog compiler and don't seem related to anything I'm doing. Ignoring the fact that my code snippet doesn't actually do anything useful, what is wrong here?
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Hey all,
I'm looking into interfacing a PSoC5LP to a bit of a strange I2C Master. Rather than being designed to run on a bus, I have to interface using SDA/SCL and an INT pin in a "point to point" configuration. The idea is easy enough, it gives a edge on the INT line, I catch it with the PSoC, and read the 9 data bytes that it sends, but there's a twist.
The catch is this device does not send an address, just the raw data bytes. How can I adjust the SI2C to account for this? I see I can use either Software/Hardware address decoding. Hardware is probably out of the question since there's just no address at all.
This leaves me with software decoding, in which case it seems like modifying the ISR in SI2C_INT.c to just drop bytes immediately into the buffer rather than doing a check on the address might work. Maybe some custom code placed in the SI2C_SW_ADDR_COMPARE_interruptStart code block in the ISR? I could maybe set the "expected address" to something that should never occur as the first byte received (would need to see if this is possible, it only has 1 bit of data, the rest are "Reserved", so maybe they'll read all 0? That would make it easy.) so it will drop into the address compare where I can drop my custom code to place the data in the receive buffer rather than use it as an address?
An easier option after looking further may be just to use the SI2C_ISR_EntryCallback(); and have it perform essentially a modified version of the stock Slave I2C code.
I'd be interested if anyone out there had any better options, maybe even something that just works in hardware?
Thanks!
Show Lesshello, I am using psoc 5lp cy8ckit-059 prototyping kit. I am planning to create a project that can switch to 3 different circuit designs/ modes which I have designed in separate projects as in attachment. Is there any methods to do this or should I just need to only use one project that combine the circuit to do this?
Show LessHi,
I'm trying to create a PSoC 58LP888 project with a parallel asynchronous input.
The host will signal on CS* and transfer 9 data bits on the rising edge of WE*.
I need to transfer these 9 data bits to memory using a DMA.
It seems to be pretty easy if you only want to use 8 bits. Just configure component cy_pins_v2_20 as an 8 bit wide input pin called "Parallel_Input". Under mapping, ensure "Contiguous" is selected and use the following in the DMA config:
CyDmaTdSetAddress(dmaTD[0], LO16((uint32)&Parallel_Input_PS), ...
Parallel_input_PS is defined in Generated_Source/PSoC5/Parallel_Input/Parallel_input.c
However, you can't use this technique with anything greater than a 9 bit input port. As soon as you go greater than 8 bits, the contiguous box must be unchecked and the .c and .h files disappear fropm the gerenated source.
I can't find any other 16 bit component that I can connect to GPIO pins and use to DMA into memory.
How can I get over this simple hurdle? I know the DMA can handle 16 bit wide transfers, it should be "just" a matter of getting the data from the IO pins into a 16 bit wide *thing* that I can point the DMA at.
Thing is, I'm "just" stumped!
Any ideas please?
Show LessHello, I am using CY8CKIT-059 prototyping kit and I am trying to use sw3 to switch my channel using analog mux. The attachment is my project. The code is working well with sw1 but when I change to sw3, the switch didn't work well as it stuck at chan 0 ( there's chan 0 and chan 1 in the project). Is there any problem with my code?
Show LessI am trying to capture a stream of bits into a buffer using a PSOC5LP board. I would like to capture roughly 40 bytes each burst at 8MHz.
This seems like a great job for a shift register and DMA.
Apparently shift registers output to a FIFO which needs to be triggered by accessing a status register before the output will update properly. Has anyone used a shift register and DMA like this before? How do you access the appropriate registers and is it possible to use a 32-bit wide shift register?
I will upload a sample project tomorrow (I have run out of work day now)
Thanks
Greg
Show LessIs it possible to create HID and CDC (UART) device simultaneously?
Thanks
Hello,
we are currently developing on a PSoC 5LP and while searching for PGA's tolerances we found out that there are 2 different values for what should be the same PGA. This values can be found in:
- Programmable Gain Amplifier (PGA) (infineon.com) on page 13
- PSoC® 5LP: CY8C58LP Family Datasheet Programmable System-on-Chip (PSoC®) (infineon.com) on page 108
We were wondering which value should we use, are they from different PGA? Maybe one of them refers to ADC buffer
Thank you in advance,
David
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