PSoC™ 5, 3 & 1 Forum Discussions
Hello,
I'm digging deeper into simulating UDBs and datapaths, using iVerilog and GtkWave. I managed to get this to work on a basic level with very simple test benches. This is ideal for me because it allows for faster component development since it's not needed to re-compile and re-flash the device after each change of the component. I wonder if other users are also simulating UDB / datapath and have some general tipps for writing the test benches.
While visualizing the waveforms with GtkWave, I recognized that some signals (internal as well as the outputs) of the UDB / datapath are in an unknown state, e.g. 'x'. Even the signals where I expected an output are in this state. I wonder if it's neccessary to setup the component in a special way within the test bench which would otherwise be done by the PSoC device.
Currently I'm especially interested in how to setup the test bench for simulating CPU access of the datapath registers and FIFOs - I'm using the FIFO in single-byte mode (holding it in reset state via the AUX register), but when I try to access the FIFO with the task 'fifo0_read' the simulation hangs.
Regards
I'd like to build this project: https://github.com/Infineon/KitProg3 on mac, but it needs PSoC Creator. Is there a way to get all of the C files generated and the verilog source synthesized once so I can move it to mac?
Show LessWhen using PSoC Creator 4.4, an invalid cm3gcc.ld is generated for a modern arm-none-eabi gcc (11.2.1)
ERROR: .cyeeprom data will not fit in EEPROM
This is fixable, however, by sticking ". = ALIGN (4);" into the .cyeeprom section of the script. But the script will be broken the next time it is regenerated.
How can I fix this?
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Hello,
I am using a PSoC 5LP (CY8C5888LTI-LP097) on a custom board. The I2C bus is communicating with another IC on the board. What I am currently seeing is a communication breakdown between this IC, likely due to a thermal shutdown on the other IC. However, the PSoC seems to react poorly to this. In most cases, the I2C commands fail and the error is caught and handled, however in a number of cases I am seeing the CPU halting due to a call to CyHalt within the I2C ISR, with the "reason" being 0.
Unfortunately I cannot upload the project files, however I have a copy of the callstack:
Can see that I2C_HP_ISR (autogenerated function) is called, then CyHalt with reason = 0. I'm stuck at this point because this is all autogenerated API code and I don't know where in I2C_HP_ISR CyHalt is being called (this issue is hard to recreate so I don't have more debugging information unfortunately).
I'd like to be able to catch and handle whatever I2C errors are happening rather than deal with a firmware crash.
Thanks!
Show LessI am trying to generate two signals with two DVDACs but I don't see any signal coming from the pins. I have had success with VDAC8 and PWM but not with DVDACs, what am I missing here?
#include "project.h"
#include "LUT.h"
CY_ISR_PROTO(isr_1);
int sineWaveSampleCount;
int triangleWaveSampleCount;
int LUT_length = 4095;
int playbackSpeedSineWave = 1;
int playbackSpeedTriangleWave = 1;
float sineWaveAmplitude = 1.0;
float triangleWaveAmplitude = 1.0;
int main(void)
{
CyGlobalIntEnable; /* Enable global interrupts. */
USBFS_1_Start(0,USBFS_1_5V_OPERATION);
isr_1_StartEx(isr_1);
DVDAC_1_Start();
DVDAC_2_Start();
/* Place your initialization/startup code here (e.g. MyInst_Start()) */
for(;;)
{
/* Place your application code here. */
}
}
CY_ISR(isr_1){
if(sineWaveSampleCount == LUT_length){ /// check if LUT is ending
sineWaveSampleCount = 0;
} else {sineWaveSampleCount++;}
if(triangleWaveSampleCount == LUT_length){
triangleWaveSampleCount = 0;
} else {triangleWaveSampleCount++;}
// sineWaveSampleCount += playbackSpeedSineWave; ///play next sample and set playback speed
// triangleWaveSampleCount += playbackSpeedTriangleWave;
DVDAC_1_SetValue(sineWaveLUT[sineWaveSampleCount] * sineWaveAmplitude + triangleWaveLUT[triangleWaveSampleCount] * triangleWaveAmplitude); ///set amplitude and mix samples
DVDAC_2_SetValue(triangleWaveLUT[triangleWaveSampleCount]);
}
/* [] END OF FILE */
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Dear all,
We are using a CY8C5868AXI-LP032 on which we have both a bootloader and a bootloadable application. We need to bootloader to check the version and type of the bootloadable application. Therefore, we use a linker script to put the .loadableVersion section at a known memory address. This known memory address is the last row of the bootloadable application. We fixed the start of the bootloadable application at 0xD000 and the total flash size is 0x40000.
This all has been working fine for quite some time, but as our image is increasing in size we encountered an issue. When the .loadableVersion is placed at address 0x1ff00 everything worked fine. However, we increased the .rodata and thereby pushed .loadableVersion just to 0x20000. (I added 56 bytes to push it over the edge.) At this point, BootloaderComponent_ValidateApplication() started to fail (With BootloaderComponent being the Bootloader component that is placed on the TopDesign. Stepping through the function, showed that the application has a size of 0x33000 bytes, which together with offset of 0xD000 means that the checksum is calculated over the entire flash including the checksum region. Therefore, the calculated checksum does not match the expected checksum. (When I removed the 56, I saw a size of 0x13000 bytes, which matches the 50 % flash usage reported by PSoC Creator 4.4).
I have tried removing the manual placement of .loadableVersion and this leads to the correct checksum calculation. However, this is not a solution as I can no longer find the application version and type that is to be checked by the bootloader.
I have the suspicion that the checksum calculation (which I expect is done by cyelftool.exe -B etc) is bothered by our custom linker script. Does anybody have a clue how I could adapt the linker script to keep the .loadableVersion section at the expected address in flash (start of last line of bootloadable) while not upsetting the checksum calculation?
I added our customization of the linker script as a zip file. I was unable to upload a file with .ld extension.
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I just bought the CY8CKIT-002 used to connect the CCG3PA. The light of the status on CY8CKIT-002 kit was working show yellow light. But our PSoC Programmer software shows failed connect with our CCG3PA board or maybe show other problems on follow picture. Would you like to give me some advice to fix that? Thank you
Show LessHello everyone,
I have a project where all the schematic resources/UDBs are used up and need to add another UART.
I am trying to explore if the UART can be changed between 8 and 9 bits on the fly to accommodate this, based on the driver code I see the following changes are required-
The clock register and the parity need to be changed after UART_Init()-
UART_Stop();
UART_Init();
UART_TXBITCLKTX_COMPLETE_REG = ((dataBits +
UART_NUMBER_OF_START_BIT) * UART_OVER_SAMPLE_COUNT) - 1u;
UART_WriteControlRegister( \
(UART_ReadControlRegister() & (uint8)~UART_CTRL_PARITY_TYPE_MASK) | \
(uint8)(uartParity << UART_CTRL_PARITY_TYPE0_SHIFT) );
UART_Enable();
Is this feasible?
Thanks!
Show LessUsing CY8C20234 PSoC 1 Capsense as a capacitance meter. It works just fine except when I added more code then the meter reading which is the IDAC reading gets a large disturbance which wrecks the measurement. The running code is exactly the same when its working compared to the non working one that just has more code in the ROM, but it's not being called. Maybe the signals in the PSoC are routed differently or maybe a ElectroMagnetic Disturbance. Is there a netlist file that can be observed to check signal routing? Any ideas what the problem might be or how to debug this?
Show LessI found PLC solution (AN76458) with PSoC 5LP.
Do you support this solution now?
And can we get a test board (evaluation board) and reference code for this solution?
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