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PSoC™ 5, 3 & 1 Forum Discussions

Anonymous
PSoC™ 5, 3 & 1
        Hello!!! I am working to get the goertzel algorithm implemented on my PSoC 5LP. I am started from one of the Filter example projects in Creato... Show More
Anonymous
PSoC™ 5, 3 & 1
        Hello!!! I am a super noob when it comes to PSoC. I am working to get the Filter_ADC_VDAC_poll example project running on my PSoC 5LP. It says... Show More
pacr_284376
PSoC™ 5, 3 & 1
 Hi,    I am using the I2C bootloader which works great.     Until now I did setup the slave adress (0x08) in the I2C component settings because I alw... Show More
ruha_285291
PSoC™ 5, 3 & 1
This may be a stupid question but as I am good at stupid here goes.    If I have a design in which I have embedded a PSoC5 device, is there any way th... Show More
GeMo_285911
PSoC™ 5, 3 & 1
Hello everybody,       I have a little problem with a PSoC1 device I am using, CY8C23433-PVXI. The documentation states that it has 256 bytes of SRAM.... Show More
Anonymous
PSoC™ 5, 3 & 1
 Hi everyone,     I am using Cy8C27443. I'm trying to write an array of int type (ADC values) to E2PROM then read back using button polling. However, ... Show More
Anonymous
PSoC™ 5, 3 & 1
The interrupt on capture box is disabled for the fixed function timer.         I assume this function is not available on fixed function timers but th... Show More
Anonymous
PSoC™ 5, 3 & 1
 Hi,    I trying to get a SPISlave to tranfer data to  an array via DMA.    It should be 2 byte per burst, with transfer count =2.Every burst need new... Show More
Anonymous
PSoC™ 5, 3 & 1
Hi,    I am considering the design of an interface device (board) that essentially will make multiple USB devices appear as one USB device.     Just a... Show More
Anonymous
PSoC™ 5, 3 & 1
I'm new to PSoC microcontrollers, and just started using the PSoC 5LP.     I'm wondering how to interpret the timer interval values captured from a ti... Show More
Forum Information

PSoC™ 5, 3 & 1

The PSoC™ 5LP, PSoC 2 and PSoC 1 Forum discusses - 24-bit Digital Filter Block (DFB), 24 UDBs, DMA controller and integrating AFE, digital logic with user interface ICs with an Arm Cortex-M3 CPU solutions.