PSoC™ 5, 3 & 1 Forum Discussions

Hi,

We are using bootloader and loadable project in our work. 

Recently we changed the bootloader TopDesign - just changed some drive modes for some pins. We encountered an issue that after we program the IO PSoC with the new code, we cannot load old IO PSoC SW via cyboot-host-i2c anymore. The output of the command are as below:

# /usr/bin/cyboot-host-i2c -v -d /dev/i2c-1 -a 0x12 -f myimage.cyacd
[main-i2c.c][160] optarg: 0x12
[main-i2c.c][161] device_addr: 0x12
CyBtldr_Program called at [Sat Jul 9 03:21:52 2022]....OpenConnection...
CyBtldr_StartBootloadOperation[TD]..inSize[7]..outSize[15]
WriteData..command[38]..count[7]
ReadData..count[15]..status[0x0]
lineLen[589]..arrayId[0]..rowNum[61]..bufSize[288]..checksum[ef]
CyBtldr_ValidateRow[TD]..inSize[8]..outSize[11]
WriteData..command[32]..count[8]
ReadData..count[11]..status[0x0]
CyBtldr_EndBootloadOperation
WriteData..command[3b]..count[8]
CloseConnection...
CyBtldr_Program failed [0x20]
Iteration[1]..Retry Count this Iteration [0]..Programming time [0]..Total Retries [0]

If I program IO PSoC with old SW, I can still load new SW via cyboot-host-i2c without any issue. 

What would be wrong?

Thanks,

Winston

Hi,

This is what I'm trying to do.

1) PSoC controls the clock as I2C Master and sends data to the I2C Slave - endpoint.

2) Right after the step 1 is completed, I2C slave endpoint would become I2C Master, send a START condition and start sending response continuously. As you might have realized, PSoC I2C component should switch to Slave mode to make this work. 

I've configured the I2C component in Multi-master-slave mode and I'm able to do Step-1. How do I go about implementing step 2 ? we don't know when EP will switch to Master mode & start sending data. How do I handle this switch and any code examples for my scenario would be very helpful.

This is my code for step 1 when I send data from PSoC master to slave EP : 

Thanks in Advance,
Srinath

Hello, everyone!

        I would like to add a component to my project topdesign in psoc Creator 4.4,  named bADC_SAR_SEQ. But this component is excluded. How can I add it to my project? 

       This component located in cycomponentlibrary.cylib dir, but excluded.

I have CAN module in my design. All initialization code is generated by Creator. It generates a macro "CAN_BITRATE" which is used to initialize module, and value depends on user bitrate selection in GUI. But, I'd like to use bitrate stored in device database, instead of this compile-time constant. Is there any way to prevent Creator to generate CAN_init()-function? And define my own CAN_init(), of course containing the same stuff as in generated one, but using my own bitrate values.