PSoC™ 5, 3 & 1 Forum Discussions
Hi,
For PSoC LP5 pin voltage, is it true that some pins are 3.3V when setting to high, some pins are 1.8V when setting to high? Or all the pins are of same voltage when setting to high?
Regards,
Winston
Show LessDear sir, It can be that the PSoC is stuck in a wrong-implemented interrupt service routine (ISR). You can find out using the debugger and/or disabling interrupt by interrupt. At least help in this regard this weekend from a humanitarian point of view. Along with spending some quality time with your family. however, there must be a loop in there that is looking for something to happen and when it doesn't that's your time out. I suggest putting a counter in that loop that increments every time it's executed and then using the debugger when the timeout occurs to see how often that loop happened. I am having all code with me (https://drive.google.com/drive/folders/1hKyy2O2HLyh9o4wxKsPFoyXOMyaorkv7) https://www.duo.uio.no/bitstream/handle/10852/82665/5/Olav-Bjerke---masteroppgave.pdf . Getting USB Time out error while replicating this into CY8CKIT-059
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Hello, I found a library for the PSOC4 that can be used to control a neopixel led strip. I tried to rewrite it for the PSOC5 but the strip is always white no matter what color I'm trying to send. Does someone has a working library or see the mistake I made?
Thanks in advance!
Show LessHello,
the PSoC5LP supports bit-banding feature. I came across AN89610, which describes the necessary steps like linker script modification, etc. Has anyone used bit-banding on PSoC5LP?
I've a few questions:
1) PSoC5LP reference manual shows that bit-banding is supported on the peripherals register section (RM rev.G, p. 42, memory map) as intended by the Cortex-M3 architecture and also mentions it in in the description of the memory map (chapter 4.3, p.41). Chapter 10 of AN89610 (rev.F, p.37) states that peripheral bit-banding is NOT supported on PSoC5LP - which one is true?
2) If the recommendations from AN89610 are used without modification, the new linker script will generate two separate RAM regions with 32kB each, with one region explicitely available for bit-banding. Is it possible to leave the original RAM region unmodified (still 64kB), create an overlapping bit-banding region AND ensure that that variables which are not assigned to that region, but placed in that region are not overwritten by variables placed in the bit-banding section? Reason for asking is because I wonder what happens if an application needs a bunch of buffers (or has a buffer > 32kB). I know it would be possible to define a smaller bit-banding region, I'm just curious if it's possible (and if yes, how it is done). It would allow to create affected variables in the usual way without giving the attribute to the bit-banding section.
Regards
We have a PSoC3 based product that is USB powered. Once in a while our customers have USB ports (generally laptops or unpowered USB hubs) that are under the 5v USB spec. We have had a few units come back bricked (sort of) when this happens. Our design has the bootloader check flags loaded into a [PSoC3] EEPROM device to determine some boot details before entering the PSoC3 app. The failure occurs when the bootloader corrupts a flag loaded into the EEPROM. The bootloader is still good, but the flags are no longer valid due to the EEPROM corruption.
Details: PSoC3 CY8C3866 in TQFP, Creator 4.4
Has anyone else seen this happen?
Thx - Steve
Show LessHi,
We are using PSoC LP5 with bootloader and bootloadable.
We have a situation that, PSoC power on another board(Let's call it core board) by setting a PsoC pin (pin30) high. When we call Bootloadable_Load() to enter bootloader mode in order to update PSoC SW, we found that the pin(pin30) changes to low for some time and the core board is powered down. The PSoC SW update is done from core board via I2C, with core board power down, there is no way to do the PSoC SW update apparently.
My question is that, when changing from bootloadable to bootloader using Bootloadable_Load(), is there a way to keep some pins unchanged? In my case, I would like to keep the pin(pin30) to be high all the time.
Regards,
Winston
Show LessHi,
We are using PSoC LP5, with bootloader and bootloadable. There are two ways to enter bootloader mode:
- Provide power to PSoC (Power on reset).
- After PSoC bootup to bootloadable, call Bootloadable_Load() from bootloadable.
How to detect by which way bootloader is entered?
Regards,
Winston
Show LessHi,
We are using bootloader and loadable project in our work.
Recently we changed the bootloader TopDesign - just changed some drive modes for some pins. We encountered an issue that after we program the IO PSoC with the new code, we cannot load old IO PSoC SW via cyboot-host-i2c anymore. The output of the command are as below:
# /usr/bin/cyboot-host-i2c -v -d /dev/i2c-1 -a 0x12 -f myimage.cyacd
[main-i2c.c][160] optarg: 0x12
[main-i2c.c][161] device_addr: 0x12
CyBtldr_Program called at [Sat Jul 9 03:21:52 2022]....OpenConnection...
CyBtldr_StartBootloadOperation[TD]..inSize[7]..outSize[15]
WriteData..command[38]..count[7]
ReadData..count[15]..status[0x0]
lineLen[589]..arrayId[0]..rowNum[61]..bufSize[288]..checksum[ef]
CyBtldr_ValidateRow[TD]..inSize[8]..outSize[11]
WriteData..command[32]..count[8]
ReadData..count[11]..status[0x0]
CyBtldr_EndBootloadOperation
WriteData..command[3b]..count[8]
CloseConnection...
CyBtldr_Program failed [0x20]
Iteration[1]..Retry Count this Iteration [0]..Programming time [0]..Total Retries [0]
If I program IO PSoC with old SW, I can still load new SW via cyboot-host-i2c without any issue.
What would be wrong?
Thanks,
Winston
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Might be for this or some other aspects.
Any one here -- Who tried to build a potentiostat with multiple CV cycles???
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