PSoC™ 5, 3 & 1 Forum Discussions
How to use semi hosting in POSC?
Hello Team,
We are using Cy8ckit-001 EVK Board and CY8C5868-LP035 module. We are trying to implement CAN module which receive and transmit data from another board. We want to achieve CAN baud rate of 250kbps. But CAN_v_3.0 datasheet says
In order for CAN component to operate properly. The accuracy of clock used (BUS_CLK for PSoC 3/PSoC 5LP) must match the CAN clock tolerance requirement which is 0.5% or better for bit-rates faster than 125kbps. But with the help of internal clock we are not able to achieve 0.5% tolerance. PSoC Creator is giving following warning.
Following is my jpeg of clock tree.
Please guide me how to configure clock tree and can module to achieve 250kbps can speed without external crystal.
Thanks and Regards,
Abhishek.
Show LessHello Every One,
I am generating 25 kHz frequency from PWM and passing it through a low pass filter with a cut off frequency 50 kHz. If I see the FFT of this signal I am getting many frequency peaks (e.g. 1kHz, 3kHz, 5kHz and so on). My PSOC IMO Clock is 48MHz. PWM clock is 1MHz. I don't !@ know the reason why this is happening.
I will Look forward to your reply!
Regards
Show LessHi every one,
I'm a french student in électronic and i have to do project for the class and i ll evaluate on it.
I'd like to create mini synthetizer .
I would like to know how could i generate tone like piano notes with the wave dac8 component?
I can't find the fonctions to set my values on the main C
I already set my frequency value for my DO note with the wavedac8
Thanks for your answer;
Best regards Kevin
Show LessHai, I am trying to evaluate the Psoc SPI functionality. I am using CY8CKIT-050 KIT for the same. I am using the SPI_Design Example under the find example project. Working with Psoc creator 3.
The display on the LCD is blank. During debugging, observed the execution halts at.
while(!(SPIS_ReadTxStatus() & SPIS_STS_SPI_DONE));
Help is sought, project folder is attached herewith.
Show LessHello everyone,
My question is related to the sample rates. What is the criteria for choosing the ADC sample rate for an arbitrary WaveDAC sample rate?
In my case, my WaveDAC (50 kSPS) is directly connected to the ADC( 17- bits; 5kSPS and actual conversion rate = 4935 SPS). Does it make sense?
Telmo Barros
Show LessHi - I have an application where I need to listen for UART traffic and send data at low baud rates.
I'd like to put the PSoC in a low power mode while those actions are taking place, but the UART doesn't operate in anything below alternate active.
Is there something I need to do differently?
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I want to configure the USBFS on a PSOC5 to simultaneously act as both a HID keyboard and as a USBUART (CDC) device. I have succeeded at making both the USBUART and the HID Keyboard configurations work independently. However, I cannot get both to work simultaneously. My intent is to use the HID Keyboard interface to send keystroke data back to the UBS Host (PC or Mac) while the USBUART interface is used as a separate channel for application configuration and diagnostics.
I have attached a export of my most recent USB Descriptor root in xml format. I have the necessary Interface Association Descriptor to link the CDC Comm & Data interfaces together. A additional interface descriptor for the HID keyboard follows the USBUART entries.
I found a Cypress document that described a similar effort, but it was written before the PSOC Creator IDE could create Interface Association Descriptors - so it's rather outdated and didn't help me achieve the desired result.
What am I doing wrong to get both the USBUART and HID Keyboard to enumerate and operate simultaneously?
Show LessHello,
This is more a thought design than something I'm actively working on, but:
I want to parse a bitstream. The bitstream contains pulses which are either aligned on a clock pulse or between two clock pulses. There is no explicit clock signal, but I know the rough clock speed and there are sync sequences embedded in the bitstream.
(It's actually the incoming bitstream from a floppy disk drive. It's MFM encoded, with an underlying clock of about 500kHz. But the details aren't important.)
It seems that the most sensible way to parse the bitstream is to trigger on the incoming bitstream pulse, and then sample on a 1MHz clock. That way I can tell from whether the clock signal is high or low about what kind of pulse it is. That seems relatively straightforward (although I'm sure the devil's in the details).
However... my bitstream isn't going to be exactly 500kHz, because it's going to be generated by ancient and unreliable mechanical hardware, i.e. floppy disk drives. So I need to somehow sync my clock against the incoming pulses. Given that PLLs are designed around synchronising against external clocks, I would naively expect to just generate the appropriate rate of clock and connect it up to my input bitstream, and it would automatically resync based on every pulse.
Is that realistic on a PSOC5?
Looking at the Clock component, I don't see any way to provide an input sync source. There are some mentions of synchronisation but nothing that looks useful. There's a Sync component, but I don't think it does what I want. Can I build a PLL out of analogue components? Can I configure the SCB to do this for me out-of-the-box? Where, basically, should I start looking?
It seems reasonable that this is possible; after all, it's basically a UART...
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