PSoC™ 5, 3 & 1 Forum Discussions
Update 8:47 PM: after looking at it with a logic analyzer, it appears the first byte of the read buffer is firing off immediately... is there no way to control the delay on the read buffer being exposed so quickly? Im running i2c at 100khz and I find it odd that I cant get in front of the byte.
Note, the CyDelay(1000)(line: 25) occurs after 0xFF in the above capture, I don't think its possible to disable the interrupts fast enough.
Original Post:
I am using the psoc5lp as a slave and when exposing the read buffer for the master, it always uses the previous value of the last transaction in index #0. I see there are other users having the same issue. I am in belief now there is is a flaw with read buffer or something is not documented correctly with the i2c component. I have attached the project to this post. I have attached an image of the bridge control showing the output, It first writes a command to slave 60 and reads back at 61. The first byte shows 0xFF while it should be 0x0A. The delay of 1 second demonstrates that there is no timing issue with the first byte being read faster than the succeeding bytes.
Reference link to another user have time same issue. PSoCDeveloper • Incorrect first byte of data during I2C Reads
Show Less#include <project.h>
#include <stdio.h>
#define I2CBUFFERSIZE 10
uint8 i2cReadBuffer[I2CBUFFERSIZE];
uint8 i2cWriteBuffer[I2CBUFFERSIZE];
int main()
{
CyGlobalIntEnable; /* Enable global interrupts. */
/* Start I2C slave (SCB mode) */
I2C_1_Start();
I2C_1_SlaveInitReadBuf(i2cReadBuffer, I2CBUFFERSIZE);
I2C_1_SlaveInitWriteBuf(i2cWriteBuffer, I2CBUFFERSIZE);
for(;;)
{
CyWdtClear();
/* Write complete: parse command packet */
if (0u != (I2C_1_SlaveStatus() & I2C_1_SSTAT_WR_CMPLT))
{
CyGlobalIntDisable;
CyDelay(1000);
for(int i = 0; i < I2CBUFFERSIZE; i++){
i2cReadBuffer = i+10; // Expected output should be 0x0A, 0x0B, 0x0C.....
}
CyGlobalIntEnable;
/* Clear slave write buffer and status */
I2C_1_SlaveClearWriteBuf();
(void) I2C_1_SlaveClearWriteStatus();
}
/* Read complete: expose buffer to master */
if (0u != (I2C_1_SlaveStatus() & I2C_1_SSTAT_RD_CMPLT))
{
/* Clear slave read buffer and status */
I2C_1_SlaveClearReadBuf();
(void) I2C_1_SlaveClearReadStatus();
for(int i = 0; i < I2CBUFFERSIZE; i++){
i2cReadBuffer = 0xFF;
}
}
}
}
/* [] END OF FILE */
I have developed an application using the USB UART for my PSoC 5LP, and I'm trying to use something like minicom on linux to talk to it. I realize linux isn't "supported" for development, but I'm not trying to program it or anything just communicate via the micro usb port. It works just fine on windows (using putty, 9600 baud), but nothing happens when I try it on linux. I've followed this tutorial but even the "loop back" doesn't work. Testing a USB-Serial Bridge Controller Configured as USB-UART with Linux® – KBA92551
When I do lsusb I see a Cypress device, and I have no errors running `minicom -D /dev/ttyACM0 -b 9600`, it just simply doesn't work. Is this possible or am I just crazy?
Show LessWe migrated our design from a PSoC Cy8C3246 to a Cy8C3466 and moved some pins in the PCB in order to optimize our hardware design for the analog parts. Now we see that the total current consumption during sleep () is elevated from 8µA in the original design to a variable range from 200µA to 1200µA. In order to be able to pinpoint the source of this current, we've built a dummy project configuring all pins in the proper mode and level acoording to the hardware design. We use a sleep mode with a 1PPS wakeup timer. The proper functioning of the sleep function is monitored using the uart_putchar() function. All hardware pins have been measured with an oscilloscope in order to detect unaccounted signal levels . Internally no devices other than the uart for debugging purposes and all hardware pins are defined in the TopDesign level. Even removing some components from the PCB did not solve the problem. Furthermore, the problem is found in all tested devices of our production batch. We suspect that the current leaks are an internal issue of the PSoC processor. What could cause this type of leaks? What precautions can be taken to prevent this leaks? And why is the leak current so variable?
Thanks in advance for your help,
Kris
Show LessIs there any way available commercially to reprogram the CY8C26443 in-situ using the ISSP protocol? Our product is expected to have a lifetime of 20+ years and we regularly receive them back from the field for recalibration, expecting to be able to upgrade their firmware to enhance reliability etc. However, it appears that Cypress does not sell a product that will do this. I have previously asked this question to Cypress both directly and via one of my suppliers' FAAs and have been told that Cypress could not suggest a solution.
The Miniprogs have never supported this chip family, even though it uses the ISSP protocol. Our old ISSP box will program them, but there's no up-to-date PC software for it and newer versions of Windows have some sort of problem with the USB the Cypress ISSP software.
Any advice much appreciated
Simon M
Show LessI have never made a custom component but find the need to bootload a PSoC5LP over a custom communication interface on our product. Does anyone know of an example that I could use rather than start from scratch and read a lot of the Custom Component Guide?
Mike.
Show LessI have run into a weird situation. I am downloading Firmware for another PSoC via USB and storing it in FLASH - later I will bootload the other PSoC with this saved firmware. To be more efficient, I am buffering the download from the USB and writing using Em_EEPROM in 256 byte chunks. At then end, I have 10 bytes left to write and when I call Em_EEPROM with that last 10 bytes, it never returns from the call and reboots! If I change the last write to 256 bytes, it writes to Flash and doesn't reboot!
Mike.
Show LessHi folks,
I'm working on a project to use a PSoC 5 MCU to add extension capabilities to a vintage pocket computer. The pocket computer uses an LH5801 CPU running at 1.3MHz.
I've set up GPIOs to read the 16 bit address bus, read and write the 8 bit data bus, and read the R/W pin. CS for the MCU is by matching 1000 from the upper four bits of address. I have also set up indexed DMA to handle data writes to the MCU memory. Basically, a status register uses some bits from the upper address to get a page offset within a 4K buffer array in MCU memory (4K starting at 0x20002000), and the lower address 8 bits provide the rest of the indexing into the buffer. I grab the buffer address when CS goes high, then read in data when R/W goes low while CS is high.
This mostly works. The problem I'm having is that I can write into MCU memory, with the correct offset into the buffer, and read the data back out, as long as the data value being written doesn't start with 1000. If the data value does start with 1000, it seems like the low pulse on the R/W line is never caught.
This is a bit bizarre for a few reasons:
1. 1000 just happens to be the CS trigger. Coincidence?
2. I have tried implementations without DMA and had exactly the same problem.
3. When I have tried implementations that wrote to a single address in memory, instead of a range of addresses, I had no problem with 1000 values (e.g. 129 or 143).
I'm really pretty stumped now. I would have thought switching to a completely different way of doing things would at least have resulted in different problems.
Any ideas what might be happening or how to further troubleshoot this?
Thanks,
Paul
Hello,
I am still working on an issue described in
PSOC5LP Jitter in interrupt handling
the problem was solved with executing a function in SRAM according to the description in
https://community.cypress.com/external-link.jspa?url=http%3A%2F%2Fwww.cypress.com%2F%3FrID%3D61932
I defined a prototype
CY_ISR(ADC_COS_ISR_LOC) __attribute__ ((section(".data")));
for the Interrupt-Service for the data from the SAR-ADU.
I ignored the compiler warning and everything works ! .... until now ...
At the moment I am using PSoC Creator 4.0 Update 1 (4.0.0.432). With the latest update ignoring the warning doesn´t work.
Now I get the following messages:
cccQkAff.s:18: Warning: ignoring changed section attributes for .data
Build error: The command 'arm-none-eabi-gcc.exe' failed with exit code '1'.
Without placing the function in the .data-section the compile process is successfully.
I wonder what to do now: In AN89610 9.4 is a statement
"Functions that are to be located in SRAM must be placed in the .data section"
this is what I have done....
Now I need a workaround for this error-message ....
with regards
Stefan
Show Less