PSoC™ 5, 3 & 1 Forum Discussions
Hello,
in the description of soc-Input of SAR_ADC, there is following sentence in the datasheet:
The first soc rising edge should be generated at least 10 us after the Component is started to guarantee reference and pump voltage stability.
How is this to understand? If I'd like to sample with 200Hz, I have to proved the first edge after 10µs? (following edges are not concern?)
Is also possible to do this first conversion via SW control to be sure to have this 10µs?
Thx,
Stefan
Show LessHello,
I am designing a firmware using PSOC creator for PSOC5LP and I would like to use SR-FF components in my design.
In my design some of SR-FF will have '0' logic on both S and R input pins after power on.
In that case what would be the output?
Many thanks.
Show LessHello all,
i have facing one problem.
a problem is my one gpio pin is turning off and same time my second gpio is turning on but both have some time difference i.e.
Gpio1 is taking the 1.4 Micro Second to turn off
and Gpio2 is Taking the 800 Nano Second. to turn on
i don't know why it is Happening ?
anybody can suggest why it is happening and how can i solve this problem.
i am using LP-035 controller.
Best Regards,
Seggi
Show LessHi,
I want to be able to modify the routing for 32 digital signals connected to 32 pins at runtime. All of them output.
User should be able to select which pin has which functionality on the fly.
Implementing this with using the PLDs consumes too much resource (I haven't tried yet but obvious.)
DSI output to pin logic has 4 to 4 mux but I need 32 to 32 mux.
As far as I understand, It's possible with manual DSI routing but the TRM not says enough info about DSI routing.
Is there any document for DSI routing and register details?
Or have you any other resource saving solution for this issue?
IC : PSOC5LP, CY8C5888AXQ-LP096
Thanks, Regards.
Show LessSomeone else asked for help with this in another thread three years ago but didn't get any useful replies, so I'm hoping I have better luck.
I have a system where an I2C device with which the PSoC is communicating may, because of a partial power failure, disappear from the I2C bus. The PSoC itself has a battery backup and shouldn't crash when this happens. Unfortunately, the following code exists in the generated I2C ISR:
else if(I2CBus_CHECK_ADDR_NAK(tmpCsr))
{
/* Set Address NAK error */
I2CBus_mstrStatus |= (I2CBus_MSTAT_ERR_XFER |
I2CBus_MSTAT_ERR_ADDR_NAK);
if(I2CBus_CHECK_NO_STOP(I2CBus_mstrControl))
{
I2CBus_mstrStatus |= (I2CBus_MSTAT_XFER_HALT |
I2CBus_GET_MSTAT_CMPLT);
I2CBus_state = I2CBus_SM_MSTR_HALT; /* Expect RESTART */
I2CBus_DisableInt();
}
else /* Do normal Stop */
{
I2CBus_ENABLE_INT_ON_STOP; /* Enable interrupt on Stop, to catch it */
I2CBus_GENERATE_STOP;
}
}
else
{
/* Address phase is not set for some reason: error */
#if(I2CBus_TIMEOUT_ENABLED)
/* Exit interrupt to take chance for timeout timer to handle this case */
I2CBus_DisableInt();
I2CBus_ClearPendingInt();
#else
/* Block execution flow: unexpected condition */
CYASSERT(0u != 0u);
#endif /* (I2CBus_TIMEOUT_ENABLED) */
}
break;
If this partial power failure happens at just the wrong time, we end up in the CYASSERT toward the end of the pasted code. There appears to be a TIMEOUT_ENABLED define that's checked for, but it's not defined so this condition hits the assert and hangs the CPU.
I could, of course just define that in my project settings, but I'm wondering if there's some setting somewhere that I'm missing that would define that in generated code.
It's also not entirely clear to me what would happen in this case with a release build where there's no CYASSERT. As far as I can tell, the IRQ doesn't get cleared in that case, so we'd end up in an endless loop of servicing the same IRQ. But again, maybe I'm missing something?
Show LessI am writing directly in assembler to get speed. Using MOVC A,@A+DPTR produces opcode 93 but the prior A value (required for the offset) appears in the accumulator afterwards rather than the contents of the eeprom addressed by the DPTR at #8000H. Normal MOVX @DPTR,A works and using INC DPTR works too. Any ideas??
Show LessHi im designing an application to use capsense buttons with psoc5 cy8ckit-059. i have fabricated a simple capsense board with five 12mm dia copper footprints each connected with a 1 mega ohm resistor. i think this should be ideal for the low end design im trying as i read somewhere. planning to use port 1 pins 2,4,5,6,7 for my 5 capsense buttons. im also using the onboard cmod capacitor. please suggest me if what im doing is correct and also the way in which i have to configure my capsense module in psoc creator. thank you.
Show LessTo all,
This may be an obvious question. I'm a bit new in USB CDC programming. However my study and empirical experiments have not make it obvious.
I want to use a callback ISR for reading incoming data using the USBUART. I can get USBUART_SOF_ISR_ExitCallback() to do what I want. It works however ...
It polls at a 1ms rate. Is there another ISR that can be enabled to process input data from the host at a much lower polling rate?
In my current USBUART configuration the following ISRs are active:
- USBUART_SOF_ISR_ACTIVE
- USBUART_BUS_RESET_ISR_ACTIVE
- USBUART_EP0_ISR_ACTIVE
- USBUART_ARB_ISR_ACTIVE
- USBUART_DP_ISR_ACTIVE
- USBUART_EP1_ISR_ACTIVE
- USBUART_EP2_ISR_ACTIVE
- USBUART_EP3_ISR_ACTIVE
Eventually I plan to convert my IN and OUT operations for the USBUART to DMA. This should solve my issue as well. Until then, if I can implement my data input reads with a less intense ISR, it would be appreciated.
Len
Show LessHi,
We use PSoC5LP to configure the capacitive button.
Although PSoC4 has an API for acquiring sensor capacitance parameters("uint32 CapSense_GetExtCapCapacitance (uint32 extCapId)"),
It was not defined in the CSD data sheet for PSoC5LP.
Is there an API to get sensor capacitance with PSoC5LP?
Please tell us how to measure sensor capacitance with PSoC5LP.
Regards,
Show Less