PSoC™ 5, 3 & 1 Forum Discussions
Use Bootlotable, Booltloader.
The contents written to the EEPROM will be lost.
How do I rewrite only the flash without changing the contents of the EEPROM?
Bootlotable、 Booltloaderを 使用します。
EEPROMに書き込み内容が 消えてしまいます。
どうすれば EEPROMの内容は変えずに フラッシュのみ書き換えれるでしょうか
Show LessI am trying to put 16bits output from the filter to the UART but keep getting corrupted results.
CY_ISR(filterVDAC)
{
char transmission[16];
uint16 c = Filter_Read16(Filter_CHANNEL_A);
sprintf(transmission,"%d",c);
UART_1_PutString(transmission);
}
Show LessHi,
We are using DMA componet of PSoC5LP.
The DMA settings used are as follows:
(a) Data transfer is individually requested using the drq terminal. (Settings required for each burst)
(b) The source address after data transfer is incremented.
(c) When the transfer of all data specified by the transfer count is completed, loop back to the same TD again.
(d) Using API of TdSetConfiguration, TD_TERMIN_EN was set to enable the trq pin of the DMA component. (Enable hardware termination)
Under this setting condition, if a positive edge is input to the trq pin after the first burst transfer request,
Is the TD in the state before the first burst request?
In other words,
is the transfer count initialized?
Is the source address pointer initialized?
Regards,
Show LessI have a PsoC 5LP (CY8C58LP-LP035) application that infrequently uses a USB connection to a PC. Most of the time the system runs disconnected from USB. I would like to be able to trim the IMO while disconnected from USB and use the USB trim while connected to a PC over USB.
It uses the internal IMO at 24MHz and IMOx2 for USB:
Is it possible to write to IMO_TR1 when the USB cable is physically disconnected?
I am pretty well stuck with the internal oscillator at this point...
Show LessHi,
I'm able to use a Timer to capture changes from a single pin. But what if I wanted to capture changes from multiple pins, using a single timer? Is there a way to do that?
Thank you.
Show LessHi all,
I am working on project that requires a I2C communication between a PSoC 5LP (slave device) and a master micro-controller. The board on which the slave device is running has 16 sensors, that are sampled using external analog muxes and the internal Delta Sigma ADC (16-bit resolution). What I would like to achieve is to place the sampled data in a buffer that can be read from the I2C master device. So far, I have implemented the following setup:
- the EOC pin of the ADC is connected to the clock input of a counter (required to change the setup the channel of the external analog muxes)
- the EOC pin of the ADC is also connected to the drq pin of a DMA (let's call it DMA_ADC), that transfers 32 bytes (16 sensors * 2 bytes) from the ADC to a buffer in RAM (adcBuffer)
- another DMA (called DMA_I2C) has its drq pin connected to the nrq pin of the DMA_ADC. As soon as the DMA_ADC has completed the transfer of the bytes, the data are transferred from the adcBuffer to the i2cBuffer
The current implementation works (I can read data from a I2C master and from the Bridge Control Panel). You can test the attached project with a single analog sensor (I typically use a potentiometer) and see the data from the Bridge Control Panel using the attached file. But I do have some questions regarding my implementation.
My first question is the following one: in order to avoid writing to the i2cBuffer when it is currently being read by a I2C master, I added a Control Register to my project. Whenever a I2C transaction (read/write) is in progress (this is detected from a I2C_EntryCallback), the Control Register does not allow to start the DMA_I2C (thanks to a logic AND with the output of the control register and the nrq pin of the DMA_ADC). Is this a correct implementation? What happens if a I2C transaction starts when the DMA_I2C has already started transferring the data?
The second question is this: I have used several I2C sensors, and most of them provided either a data-ready pin or a status bit in some register that allowed to determine if new data could be read from the sensor. What would be, in your opinion, the best way to implement such a thing on a PSoC-based slave device?
Please find attached my current project implementation for the slave device, and a file that you can use with the Bridge Control Panel to test the project.
It's the first time that I make such use of I2C and DMA, so I apoligize if these are silly questions.
Thanks,
Davide
Show LessHi,
I am development an application that save in eeprom some data with Psoc5. When i update the firmware with the bootlader host some times when the firmware start, i found the some eeprom cells resetted. I have seen this problem because i found, after power-up, the variables saved in eeprom resetted abnormally. After update the firmware, turning on and off the board this problem don't verify never again. In fact the variables aren't longer reset in a strange way. Why there are this problem that the eeprom cells some times are resetted after i update the firmware ? i repeat this problem doesn't verify always, but some times.
Best regards
I am trying to use a PSoC5 in a project where it will be controlling a chip that uses it's own 28-bit parallel bus. How would I go about representing a non-standard (as in non SPI, I2C, etc.) type of bus on the PSoC5? Do I need to connect each of the 28 lines from the chip to an I/O pin on the PSoC? Has anyone done something like this before? The data sheet for the component I am trying to work with is here: https://ams.com/documents/20143/36005/TDC-GPX_DS000321_1-00.pdf/0b5268df-ea27-b5c6-87cd-e8605aa2c819
Thanks in advance!
Show LessHi,
These are some the forum threads I have read before submitting this question:
Bootloading from SPI / I2C memory (?)
bootloader/bootloadadle from external memory
PSoC 4 EEPROM Bootloader Example - Hackster.io
This is the documentation I have studied:
- 001-60317_AN60317_PSoC_3_and_PSoC_5LP_I2C_Bootloader
- 001-73854_AN73854_PSoC_Introduction_to_Bootloaders
- CY_BOOT_COMPONENT_V5-50_5lp
- PSoC_Creator_Component_Author_Guide (chapter 10) - this is the only documentation I could find on "custom bootloader"
Here is the general idea:
- I am developing a product using PSOC5LP which has an external I2C EEPROM.
- This EEPROM is 2Mbit, but a large portion of the memory is used up for other things.
- I have converted the contents of the .cyacd file generated at compilation to a .bin file which will be used to perform an over-the-air update. This .bin file is 256 bytes per line, and will be written to EEPROM a page at a time (256 bytes/page). I will do my own checksumming and data integrity during the write process to EEPROM. I do not wish to use Cypress's checksum features, etc. The .bin file contains only firmware data, and nothing else.
- The importance of not writing additional .cyacd information to EEPROM is both due to minimization of overall data transferred over the air, as well as memory used in EEPROM.
- The data needs to be stored in EEPROM first, not in flash.
- The data needs to be stored as binary data only, without checksum information, etc. so it is aligned to each page in EEPROM.
Question:
In bootloaders I have used previously, you write data to flash memory, do any checksums, etc. as needed, verify the write completed, continue until all data is written to flash, and then reset the chip (and sometimes you may swap a flag to revert to previous code if there's a flash write error somewhere in the middle of the process).
I'm having difficulty understanding the process for implementing a custom bootloader to read data out of an I2C slave device, write it to flash, and reset the chip. All of the examples I have seen seem to indicate there's a host present somewhere sending commands and receiving responses. In my case, the PSOC5LP micro is the host, with an I2C master in the bootloader code taking data out of external memory and writing it to flash.
My understanding is that there are 5 functions that need to be implemented:
void CyBtldrCommStart(void) - this function starts the I2C master
void CyBtldrCommStop(void) - this function stops the I2C master
void CyBtldrCommReset(void) - this function resets data pointers (clear cached data, etc.)
cystatus CyBtldrCommWrite(uint8 *data, uint16 size, uint16 *count, uint8 timeOut) - this function would technically write data to a host, but what if the "host" is an EEPROM slave device ?
cystatus CyBtldrCommRead(uint8 *data, uint16 size, uint16 *count, uint8 timeOut) - this function reads data from EEPROM device -- I assume that Cypress state machine is going to write contents of data to flash here?
In my case, there is no concept of CyBtldrCommWrite, because the host would only be communicating with itself. Or maybe, I'm very confused.
I need some help in understanding the concept of reading from EEPROM, writing it to flash, and resetting the micro from a custom bootloader. Is this functionality supported within the bounds of these 5 functions?
Thanks
Show LessEspecially thanks to motoo tanaka for testing out my basic test program. I simplified the test program even more, but still get compiler failure. This time I just took exactly what you wrote, but left out the printing part. The following is a copy, including the error messages. This should work. I just don't understand.
#include "project.h"
#include "math.h"
double A=1.0;
double B=1.0;
uint8_t n ;
int main(void)
{
for(;;)
{
for (n = 1 ; n <= 10 ; n++)
{
B = exp(5.0 / n) ;
if (n == 10)
{
A = 1.0 ;
B = 1.0 ;
}
}
} *****this is the line number 22 that the error message refers to
}
/* [] END OF FILE */
ERROR MESSAGE ARE AS FOLLOWS
OK. So the messages I get are as follows:
"collect2.exe: error: ld returned 1 exit status"
It also said " The command 'arm-none-eabi-gcc.exe' failed with exit code '1'. "
It also said this in the notice list
"build error: undefined reference to 'exp' line 22" (I marked line 22 so you could see what they were referring to. Don't know how to copy the listing with line numbers included)
So how come this fails to compile ? Such a simple program. As before, using psoc5lp board and creator version 3.3
Show Less