PSoC™ 5, 3 & 1 Forum Discussions
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Hi,
I need to know the details mentioned below.
CY8C5868LTI-LP039 part is currently in production, how long this part will be supported, any plan for EOL for this part?
Show LessDear Sir
we are working with the CPU CY8C5667AXQ-LP040.
we have boards with CPU from 2019 and we use the ADC 12 bit
The transfer function from analog voltage to digital number is not the same as with new components from 2020.
Do we need to calibrate the A2D in each CPU?
If yes is it gain and offset that needs to be calibrated?
can you kindly send me link to reference or white page or software sample for this issue
thanks
avihoo keret
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Hi,
This is to announce Sync32 custom component in the Community Code Examples. It is small utility component which can directly substitute standard Sync component while occupying much smaller footprint on the schematic.
Sync32 custom component for PSoC5 and PSoC4
odissey1
Figure 1. Left - original schematic using standard Sync, Right - schematic modified using Sync32.
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For all those interested,
I've upload a project for the PSoC5 that user-interactively modifies the IMO or the ILO internal RC clock trim registers.
PSoC5 IMO and ILO clock trimming Project.
It may have educational value to the designer that needs to have improved internal RC clock accuracy without resorting to an expensive system crystal. This project does require the lower-cost watch crystal (32.768KHz) as the accuracy reference.
Len
Show LessI'm trying to edit an existing component to replace a hardware digital input pin with a digital input terminal, so I can control it from my schematic directly, rather than connecting it to a hardware GPIO. But how do I access the value of the terminal from inside the component? It doesn't have a read() function like a pin does? Do I need to connect it to a control register or something? All it does is read a true or false value from the surrounding circuit.
It would be simpler if I didn't need the terminal at all. Is there a way to have a component get a truth value from the containing schematic/program other than using a terminal? Maybe the component exposes a function that lets the containing project modify it's internal state? But the opposite would be better: if the component could query the containing project's state.
Show LessHi Team,
I am using serial port- DB9 connection. I am using below code. But i am getting the below output.
int main(void)
{
uint8_t c;
CyGlobalIntEnable; /* Enable global interrupts. */
UART_Start() ;
UART_PutString("\x1b[2J\x1b[;H") ; /* clear screen */
UART_PutString("This is an ECHO program\n\r") ;
for (;;) {
c= UART_GetChar();
if(c=='L')
UART_PutString("Light");
else
UART_PutString("Dark");
//if (UART_GetRxBufferSize() > 0) { /* received some data */
// c = UART_GetByte() ;
// if ((c != 0) && (c != 0xFF)) {
// UART_PutChar(c) ;
// }
// }
}
}
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Greetings,
We are using CY8C5888AXI-LP096, which P4_2, P4_3, P4_4, P4_5, P4_6 GPIOs are configured as camera power enable pins. Basically, they are connected to the base of a bipolar transistor (MMBT3904TT1G), which activates SI2399DS-T1-GE3. The latter, in turn provides 3.3V to the cameras. At elevated temperatures (above the max rated temperature for these cameras), cameras stop being detected. We probed the power enable pin and discovered that it stayed low. We assumed that the PSoC was trying to protect its GPIOs from wither over-current or over-voltage.
We didn't understand, however, why this interlock was activated for ALL these GPIOs (P4_2, P4_3, P4_4, P4_5, P4_6) though only one of the cameras got over-heated. Any ideas?
Show LessHi everybody,
I'm coding a adc lecture (14 bits) to SRAM with DMA. The idea is, save the row size of flash (255 bytes) first on the SRAM. When the transaction is complete, move the SRAM data to the flash.
The problem is simple, i got mi DMA configured on 0x1fff8000, so i will use to 0x1fff80ff, but using the transfer count with 255 bytes, crash the program, but using around 60 transfer count never crash on the debug process (the data limit it's 4096 if i'm not wrong).
The next step it's stop when the 255 bytes are wrote on SRAM for later write to flash using CyWriteRowData();
Regards and thanks in advance,
Xavier.
Show LessI want to shift *a lot* of bits out in a steady stream (without gaps between the bits).
So I set up a Shift Register for a test. I set it up to be 32 bits. I sent the output into a pulse convertor to get a 2us pulse out no matter the width of the input pulse.
I then ran the DMA AN52705 project and realized that was not what I wanted. (too long between bits, plus some suspicion of when the bits went out)
I then set up a single shift register for 32 bits and wrote 0x55555555L into it. I got 16 pulses. good.
So then I tried reading the Fifo, which the *Documentation* says is there.
After much experimentation, the Shift Register Documentation is wrong. You do not get an input fifo unless you use the Load signal. If you use the Load signal, you must programmatically control the loading of the Shift Status Register when the shift has ended. There are no indications the shift has ended from the component, as the "Store" signal must be controlled programmatically also.
About the only way to really use the component is to make sure you don't select the load and store signals, and put a lot of hardware or firmware around the shift component to provide you with an indication of when the shift has ended so you can either generate a load pulse or programmatically load the shift register.
Has anyone done this?
Show Less1. USBUARTの受信バッファは
USBUART receive buffer is,
(a) 何Byte有るでしょうか。
How many bytes is it?
(b) そのバッファー数は、マクロか何かで知ることか出来るでしょか。
Is it possible to know the number of buffers with a macro or something?
(c) そのバッファー数を変える事可能でしょうか。
Is it possible to change the number of buffers?
2. USBUARTは受信で割り込みを発生できるでしょうか。
Can USBUART generate an interrupt on receive?
Best Regards.
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