PSoC™ 5, 3 & 1 Forum Discussions

Initially I defined to use a PSOC 6 (development kit including wifi+BLE) but I discovered that the ADC SAR has 12 bits of resolution. As I suppose this resolution is fixed, I was trying to discover other PSOC with a higher resolution and I found PSOC 5LP 58LP, which allows 8 to 20 bit delta-sigma ADC. Good, but I can not find clearly which is the number of analog channels to be read, and if I can have a kit having also capabilities for wifi+BLE. So these are my questions:

1/ max number of analog read channels for PSOC 5LP CY8C58LP (kit CY8CKIT-050). Any code example on how to route many analog channels to the ADC?.

2/ How could I expand CY8CKIT-050 with wifi+BLE capabilities

Thanks for the help.

I am designing pcb board that use CY7Y64215 28-pin ic (psoc1 family). I want to use mini USB type B to program and debug the ic.Is that possible or I have to use Miniprog3?

Hi, I am trying to build a system where I can can create two sine waves with arbitrary Phase shifts, which i can control in the code. I am using the DDS24 component created byBoTa_264741​ as a clock source for the DMAs which will send the sine wave table data to the VDAC. The DDS24 component works well, but i am confused as why using the phase shifted signal from the DDS24 to send requests to the DMA which will then send data to the VDAC will not result in a phase shift in the output of the VDAC. Any guidance on what i am doing/thinking wrong is greatly appreciated. I have attached a photo of the DDS24 output, VDAC output and the schematic.

Hello

Thank you for your constant support.

・Interrupts generated in the interrupt-disabled section are pending and resumed after exiting the interrupt-disabled section.

・Due to the specifications of Coretex, only one of the interrupts generated in the interrupt disabled section has the highest priority is pending.

Question１

Is my perception correct?

As far as the driver source code is concerned, interrupts

Registers representing pending are for each interrupt number

It seems that bits are assigned, so I feel that all types of interrupts can be pending at the same time.

Specifically, even if I experiment with the following code, it seems that the UART n transmission buffer Empty interrupt is being executed.

UART_XXX_PutChar (a); // Write here to the transmit register of UART n

State = CyEnterCriticalSection ()

UART_XXX_SetPending (); // Set a UART m (priority is higher than n) interrupt, separate from UART n

Wait processing of about 100 milliseconds // The first UART n transmission buffer Empty interrupt should have occurred so far.

CyExitCriticalSection (State);

Question2

Why are low-priority interrupts entered within the interrupt-disabled section also pending?

Question3

Does it exist if the generated interrupt is discarded?

Since the customer is in trouble, it would be helpful if you could reply as soon as possible.

Best Regards

Hayato

Hi there,

I am looking for any guidance on how to start using adafruits GPS module with PSoC 5LP as i could not find any useful sources online. Any guidance is much appreciated. Thanks !

Hi all,

I am working on an RC car project and for this project I am using a multitude of sensors (speed, GPS, Proximity). So far, I've been running through a single while(1) loop, however, I've been thinking about exploring the possibility of using FreeRTOS to manage all the sensors in the system. (I have no experience using RTOS but I would like to start somewhere)

Now, this uses radio communication over UART in order to receive the commands for the car's movement.

My question is: Would you recommend using an RTOS for something like this?

Hi,

In my board design I have connected these 2 analog pair inputs to the SIO pins in the PSoC:

AIN_O6P = P12_2

AIN_O6M = P12_3

*M refers to GND path which belong to this specific analog input.

*P refers to the analog input.

Please your support understanding how to configure these SIO inputs.

Thanks,

Roy Roif