I am trying to understand the timing of DMA transfers in the PSoC5LP in as much depth as possible, in particular DMAs between SRAM and the UDB working registers. So I set up a project to play around with these, routed signals that I was interested in to the device pins, and hooked up a logic analyzer so I could see the timings.
One thing that surprised me was that a DMA burst to a UDB control register always took two cycles for a write. Digging through the TRM I found a reference to the register(s) WAIT_CFG which controls wait states for access to UDB registers. Sounds promising. In the Registers TRM you can find out what the bits mean, but I found no further information. Disabling the wait states for the UDB working registers had the desired effect and the DMA timings were now as expected (7 cycles from drq latch to first write, 1 cycle per write).
So all is well? This is the question really. I have no context information at all. Under which conditions (e.g. bus clock speed) is which wait state setting acceptable? Is it automatically configured somehow? (appears not, I always get one wait state whether I set the bus clock to 200kHz or 72MHz). What other tradeoffs are there?
Obviously it would be nice if accessing the UDB registers was always without wait states, but there is probably a reason the wait state control is there and defaults to 1 for the working registers. Please tell me if you know more or where I can find such information.
Thank you. Thinking about it some more it makes sense that if you can get by with 1 wait state at 80 MHz, then it should be safe to do away with it at 40MHz since the signal gets the same amount of time or more.