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PSoC 5, 3 & 1

Anonymous
Not applicable

I want to be able to eventually do a series of UDB state machines which autofill the FIFOs and once full process, request another burst etc...

   

I set my FIFO's appropriately (at least I think): 

   

    /***** SET UP FIFOs FOR WRITING TO *****/
    interruptState = CyEnterCriticalSection(); 
    //Clear FIFO status
    (* (reg8 *) rgb_control2_1_Pixel0_u0__DP_AUX_CTL_REG) |= (1);
    (* (reg8 *) rgb_control2_1_Pixel0_u0__DP_AUX_CTL_REG) |= (1);
    //Set FIFO levels to "At Least Half Empty" meaning bus knows two bytes can be written
    //May need to remove and set to 4 bytes depending on how the request handles...
    (* (reg8 *) rgb_control2_1_Pixel0_u0__DP_AUX_CTL_REG) |= (1 << 2);
    (* (reg8 *) rgb_control2_1_Pixel0_u0__DP_AUX_CTL_REG) |= (1 << 2);
    //Allow FIFOs to run again
    (* (reg8 *) rgb_control2_1_Pixel0_u0__DP_AUX_CTL_REG) &= ~(1);
    (* (reg8 *) rgb_control2_1_Pixel0_u0__DP_AUX_CTL_REG) &= ~(1); 
    CyExitCriticalSection(interruptState);

   

And then inside a loop and debug mode, I write data to the FIFO's, which it takes in and I can read back the correct value from it. The "blk_stat" will assert (low to my pin) once two bytes are written, however, the bus_stat does nothing regardless of how much I write to the FIFOs, clear the FIFOs, etc... 

   

        for (i = 0; i < 4; i++){
            CY_SET_REG8((reg8 *) rgb_control2_1_Pixel0_u0__F0_REG, test_pixel);
            j = CY_GET_REG8((reg8 *) rgb_control2_1_Pixel0_u0__F0_REG);
        }

   

Any insights on settings I might be missing here in order to get the bus_stat to do anything other than remain high? In my datapath  I have : 

   

.f0_bus_stat(dp0_fifo0empty),   AND .f0_blk_stat(dp0_fifo0lcl),  with both wires assigned to drive output pins for viewing...

   

Neither signal will trigger a state transition and subsequently the instruction which moves F0->A0 and consumes the FIFOs contents.

   

CFG15 has both F0 and F1 as BUS - should I change one? Is there something else necessary in an aux register or initialization I'm missing? I've poured over this for about two days now and am stuck.

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9 Replies
Bob_Marlowe
Expert II

I am not quite sure, but in

   

            CY_SET_REG8((reg8 *) rgb_control2_1_Pixel0_u0__F0_REG, test_pixel);

   

what makes you think that rgb_control2_1_Pixel0_u0__F0_REG is a pointer to a gegister?

   

 

   

Bob

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Anonymous
Not applicable

A couple of verifications :

   

1)It's assigned in cyfitter.h ---> #define rgb_control2_1_Pixel0_u0__F0_REG CYREG_B1_UDB05_F0

   

2) I can successfully write and read a value from it in software without any issue and have it return the correct value with whatever values I set in test_pixel.

   

3) And because writing two or four times to it, depending on how the FIFO settings are configured will set bus_stat flag which I have attached to a pin and viewed on a scope. If the software reads were interacting with the FIFO pointer in some way, the bus_stat flag in the DP wouldn't set.

   

The blk_stat flag does nothing from what I have seen when attaching it directly to wire assigned to an output, and nothing when wiring it a register, wired to an output pin. It also does nothing to effect the state in my verilog code whereas the bus_stat when used locally, will.

   

There has to be something wrong in the FIFO settings but I have isolated almost every variable possible.

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Bob_Marlowe
Expert II

Debugging verilog components can be a pain in the ass.

   

Can you please post your complete project including the verilog component, so that we all can have a look at all of your settings. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file. I am not an expert concerning verilog, but I'll have a look at.

   

When all fails get in contact to Cypress directly: At top of this page select "Design Support -> Create a Support Case" and describe your problem, attach your project. Project information will be kept confidential.

   

 

   

Bob

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Anonymous
Not applicable

What I'm gathering from reading deeper and deeper is that there is no way to load A0 or A1 with a FIFO directly - I have to load the FIFO to D0/D1 from the FIFO using a load signal. The DP object has no signal for A0 or A1 load, only F0/F1 for output in cases of dynamic use? A0/A1 are not automatically consuming the FIFO despite having a bus input setting so I guess that doesn't actually happen - looks like A0/A1 only load from the UDB system bus...? Any way around this? I have tried the datapath instruction with A0 = F0 and the conditional waiting for an empty FIFO loops infinitely regardless of bus or blk status. The accumulators don't seem to be able to consume the FIFO despite some of the graphic depictions showing otherwise.

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Bob_Marlowe
Expert II

Seen this?

   

 

   

Bob

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Anonymous
Not applicable

Yes, the TRM, Datapath Config Tool, Advanced DMA doc, etc... still no dice on getting the FIFO to be consumed. Will probably open a ticket.

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Anonymous
Not applicable

I have a similar problem. Trying to get DMA from SRAM to FIFO to work but no success An example of using DMA with FIFO would be very helpful. Best in 8-bit and 16-bit mode...

   

I am using load D0 with F0 for ALU processing

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Anonymous
Not applicable

I got an email from Todd Dust who is an applications engineer about a document survey and he asked what projects I would like to see come down the pipeline on advanced FIFO usage, and this is what I'm going to suggest.

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Anonymous
Not applicable

Hmm, that would be very interesting. Meanwhile a spent a lot of time into the DMA transfer problems and now i believe there is a HW bug in the DMAC (or a very tricky configuration as workaround). See http://www.cypress.com/forum/psoc-5-device-programming/tx-dma-datapath-fifo-register-dod1.

   

 

   

Means i would like to see a Demo Implementation (with TD's running in a loop) very much also.

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