I have been using the 1.20 UART on an RS-485 bus configuration and the network ceases to operate when undating to 1.50 (I changed the number of bits setting after the update, but nothing else).
When I put a logic analyzer on the bus it looks like the 1.20 version introduced a slight amount of inter-byte delay, as indicated by little pulses on the Tx Enable line, but this is not so with the 1.50 version. I am only sending about 12 bytes in a typical packet, but this seems to be long enough for differences in the baud rate clocks to create a CRC error.
When I stop using buffered transmission and thus introduce a small inter-byte delay, the network operates as before.
What I would really like to be able to do (and have for the last 10 years) is set the number of stop bits for Tx to 2 and set Rx to 1. This would be a simple way to still use buffered transmission and get a little delay for re-framing each byte. There may be a way to select an inter-byte delay through the API, but I haven't found it.
I'm curious if others have faced the same situation, and what some possible solutions are. Plus if enough chime in, may Cypress will address this...
UART component has 4 bytes of hardware FIFO. Since you are using 12 bytes of data as a packet, there is a an ISR running under the hood which takes care of handling the interrupt. The extra buffer size (greater than 4) is implemented in the RAM available.
You can try out the following methods to get the communication working:
1) Since ISR is used, try increasing the BUS clock to 12MHZ or 24MHz (in case it was initially set to 3MHz) in the clocking tree. This will make handling of ISR's faster.
2) Using the APIs which use Blocking method of transmission is helpful when packets of data are being transmitted. This eliminates the need for Delays in between the data bytes.