Hi every One,
In my previous post, i had mentioned the existance of Count7 counters in PSoC UDB. I would like to add more on that. There is a terminal count signal that is coming out from the count7 counter. This terminal count is available in 2 forms, one the unregistered version and the other one is the registered version.
To select between the two, we will just have to use the cy_alt_mode. When the cy_alt_mode is " False" , the terminal count signal coming out is registered or delayed by a clock cycle. This means that we will get the terminal count signal, when the count reaches the "cy_period_value" , 127 in the default case.
When the cy_alt_mode is made "TRUE", the terminal count signal is issued when the count reaches the value "Zero".
happy designing,
Rahul Ram.
