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PSoC 5, 3 & 1

Anonymous
Not applicable

I am trying to understand as much as possible the component APIs and status registers.  I am working on the control of a TFT LCD based on the ST7735S driver.

   

Looking at the status registers in the datasheet, it is not clear that there is one status bit that positively reflects that both TX software buffer and TX FIFO have been fully transmitted and that the SPI transmit operation is fully completed.   I am under the impression that the register bits are exclusively controlled by the SPI Master state machine.    If that is so, safe check for completion of a five byte transmission should require a loop like

   

   while( ! SPI_DONE  |   !(GetTxBufferSize() == 0)  ) 

   

Am I right ?

   

I am asking this because I have seen in some examples just waiting for  SPI_DONE.    Is this a case of  "good enough" vs. 100% sure ?

   

Tony  

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1 Solution
Bob_Marlowe
Expert II

You may use  SPIM_STS_SPI_IDLE

   

Datasheet says

   

SPI IDLE: Set when the SPI Master state machine is in the IDLE State. This is the default state after the component starts. It is also the next state after SPI Done. IDLE is still set until Tx FIFO Not Empty status has been detected.

   

 

   

Bob

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Bob_Marlowe
Expert II

You may use  SPIM_STS_SPI_IDLE

   

Datasheet says

   

SPI IDLE: Set when the SPI Master state machine is in the IDLE State. This is the default state after the component starts. It is also the next state after SPI Done. IDLE is still set until Tx FIFO Not Empty status has been detected.

   

 

   

Bob

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Anonymous
Not applicable

Bob, my point is that the SPI Master state machine does not know anything about buffer content, so relying on SPI_DONE of SPI_IDLE implies that interrupt process runs perfectly, timely and with no misses.    May be SPI_IDLE fits "the best that can be done".   That said, I will use SPI_IDLE.

   

Thank you

   

Tony

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