After reading through the "Psoc 3 and 5LP interrupts" document, I get the impression that interrupts cannot be nested. However, the document does not seem to come out and say this. So, for clarity:
If a low priority interrupt is being serviced, and a trigger occurs for a high priority interrupt, the high priority interrupt won't be serviced or activated until after the lower priority interrupt is finished? However, it will be next in line?
Moreover, if two or more interrupts of higher priority occur in short succession, will interrupt controller remember these interrupts and service them in order of priority? For instance, given servicing a low level "7" priority interrupt, a level "6" interrupt is triggered, then a level "5" interrupt (5-1), then another level "5" interrupt (5-2), all while the level "7" is still being serviced. Will the ISR controller service these interrupts in order of the highest priority level, and then order they were received: service the first "5" interrupt (5-1), then the second level "5" interrupt (5-2), then the level "6" interrupt?
There is an ARM Cortex M document telling exactly that an interrupt of lower priority that is under service will always be interrupted by a higer priority interrupt. This sounds reasonable or what else should be the priority be good for.