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I am using two PSoC 5LP with two different sketches. The first PSoC simulate some SPI-Data-Transfer and the second should receive all Data.
The RX-Buffer should be cleared by the DMA. The SPIS-Rx-Int. is set on "Interrupt when FIFO not Empty".
The problem is that the Slave only receive the first Byte (Picture 1) and wont reset the Rx Interrupt (Picture 2).
My Sketch based on the SPIM/SPIS-DMA example from cypress.
CH8= DMA_Tx_Master
CH9= DMA_Rx_Slave
CH10=SPIS_Rx_Interrupt
Did i forget some SPI config?
Is the timing for the SPIS-Interrupt correct at the 8th clock-rise?
Is there some kind of SPI-continously-receiving mode?
Solved! Go to Solution.
- Labels:
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PSoC 5 Device Programming
-
PSoC 5LP
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Hi Eddi,
It looks like the descriptors are not chained properly.
In function Dma_S_Rx_Configuration(), modify the following,
CyDmaTdSetConfiguration(S_RxTD[0u], 1, S_RxTD[1u] , TD_TERMOUT0_EN|TD_INC_DST_ADR);
CyDmaTdSetConfiguration(S_RxTD[1u], 1, S_RxTD[0u], 0);
Also, SPIS_RX_STATUS_MASK_REG=1 (in ISR) and SPIS_EnableInt() (in main) are not necessary.
If "Interrupt on Rx FIFO not empty" is enabled in the SPI configuration window, it will automatically take care of the interrupt enable.
Thanks,
Shanmathi
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Hi Eddi,
It looks like the descriptors are not chained properly.
In function Dma_S_Rx_Configuration(), modify the following,
CyDmaTdSetConfiguration(S_RxTD[0u], 1, S_RxTD[1u] , TD_TERMOUT0_EN|TD_INC_DST_ADR);
CyDmaTdSetConfiguration(S_RxTD[1u], 1, S_RxTD[0u], 0);
Also, SPIS_RX_STATUS_MASK_REG=1 (in ISR) and SPIS_EnableInt() (in main) are not necessary.
If "Interrupt on Rx FIFO not empty" is enabled in the SPI configuration window, it will automatically take care of the interrupt enable.
Thanks,
Shanmathi
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Hey Shanmathi,
thank you for your comment.
This change solved the Interrupt Problem.
best regards
Eddi