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PSoC™ 5, 3 & 1

Not applicable

I know that the Analog Ground Bypass capability is enabled via the Global Resource field AGndBypass in PSoC Designer. What I am a little murky about, though, is what the setting of pin P2[4] should be. I know that in cannot be set to ExternalAGND, as this would then defeat the Analog Ground Bypass capability. By default, P2[4] is set to select StdCPU with a drive of High Z Analog. Is this the setting that pin P2[4] should be left at? It seems a little confusing, as StdCPU implies that Port2 would drive the pin. Then again, with the drive set to High Z Analog, it would tend to imply that the pin is under analog I/O control. I've already looked at the TRM, AN2219, AN2221, and AN2224, but I have yet to achieve complete clarity on the issue.


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