I know that the Analog Ground Bypass capability is enabled via the Global Resource field AGndBypass in PSoC Designer. What I am a little murky about, though, is what the setting of pin P2 should be. I know that in cannot be set to ExternalAGND, as this would then defeat the Analog Ground Bypass capability. By default, P2 is set to select StdCPU with a drive of High Z Analog. Is this the setting that pin P2 should be left at? It seems a little confusing, as StdCPU implies that Port2 would drive the pin. Then again, with the drive set to High Z Analog, it would tend to imply that the pin is under analog I/O control. I've already looked at the TRM, AN2219, AN2221, and AN2224, but I have yet to achieve complete clarity on the issue.
Following settings are required to be made -
1. Pin P2 drive mode should be set to High Z Analog. This disables digital input buffer and also disables digital output circuitry associated with pin P2.
2. AGndBypass setting (in Global resources) should be enabled. This routes the internally generated AGND voltage to pin P2 through internal 8.1K resistor. You need to connect capacitor externally to implement low pass filter. See section "Analog reference" in TRM.
StdCPU allows CPU to take over port pin control. But the effect on the port shows up only if the drive mode is set to strong, slow strong or resistor pull up/down. When the pin drive mode is set to High Z analog, digital output and diinput circuitry, associated with that particular pin, are disabled. Thus, if the CPU writes into port data register, it will not cause any effect on the pin.
One thing to note here that a pin is always available to be routed to internal analog circuitry, irrespective of drive mode settings. You can see this in "GPIO Block diagram" in "General Purpose IO" section of TRM.
Having said that, when using a pin for analog purpose, its drive mode should be set to High Z Analog, so that the digital output circuit doesn't interfere with analog function.