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Are you talking about PWM2 duty cycle = PWM1 duty cycle * 0.5 ?
If so, you can set PWM2's compare value accordingly each time you set PWM1's duty cycle.
Bob
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Thanks for your reply: Please refer to attached picture, maybe you can understand
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There are 2 PWMs and both of them have 50% duty cycle but their mutual offset(or delay in the start of one waveform wrt to other one) is variable from 0-50%.
I am using it to drive Bi-Directional DC-DC Voltage Converter
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OK, now I understand that you want to have a phase shift (sorry for the language barrier).
Just thinking over I would use two PWMs running from the same clock. Some counting logic must be used to skip clock pulses for either of the PWMs to get the phase shift. There is no direct solution I've got at hand, but the available hardware logic within a PSoC5 will be quite enough to handle that. You even (when some more acquainted to PSoCs) may generate a self-written component using a hardware description language (VeriLog) that is performing the job.
Bob
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muhammad,
there is an approach to generate variable phase shift between TTL pulses (untested):
http://www.cypress.com/file/37261/download
There is another approach using DDS generator with dual variable phase output. You may download it from this thread:
and here:
http://www.cypress.com/forum/psoc-5-device-programming/need-demo-program-lock-amplification
YouTube link:
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Congratulations and thank you for sharing your project.