PSoC5LP DMA 2-byte transfer from SRAM to Control register

[MiNe_85951]

Hi,

We are considering the connection between a 16-bit parallel IO ADC and PSoC5LP.
Therefore, PSoC5LP needs to output 16-bit to GPIO.

We understand that one control register is 8-bit, so two control registers are needed.

Therefore, two DMAs are also required too.

For example,

Define a variable called DATA with uint16,

DMA1 : 16bit DATA of SRAM => HI8(DATA) to Control Reg1

DMA2 : 16bit DATA of SRAM => LO8(DATA) to Control Reg2

We are thinking of the above configuration.

Is it possible to divide 16-bit DATA into HI8 and LO8 in DMA configuration?

Or do We have to DMA transfer after dividing the variables into HI8 and LO8 in firmware?

As a point that we care about,
Does a time lag occur when using two DMAs?

Please let us know if there is another best way.

Regards,

[odissey1]

user_23...

Please clarify: it is either (1) you have an ADC with output bus, which needs to be sampled by PSoC;  or (2) you have a DAC with bus input, which takes data from the PSoC. From your description it is hard do deduct what is going on. The best is to provide a part number.

/odissey1

[RodolfoGL · Accepted solution]

There are ways to place the control registers side by side, so you can use one DMA transfer. Refer to this post:

Can be expanded control register component to 16bit or 32bit? (That meaning is not to use two contro...

[MiNe_85951]

Sorry, It's my mistake
It is not ADC but DAC.

Connect PSoC 5 LP and 16-bit DAC with parallel IO.

[odissey1]

user_23..

There is FIFOout component available, which was developed for fast parallel data output to the output bus. See #8 of thread:

Re: Is a FIFOout component available?

It can be used with either CPU write or DMA transfer from RAM buffer. It utilizes 16-bit UDB 4-word deep FIFO buffer to smooth out transfer.

/odissey1