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Hi,
Is there a way to implement a counter with micro-second resolution without calling a ISR?
In my ideal world I'd read a register, and the register will return a 32-bit number... and that register gets incremented "auto-magically" once per milli-second.
I'd like to avoid calling an ISR every millisecond just up update a variable.
Is that possible?
I know that I can use SysTick + callback (or SysTick without a callback, but I'd like to avoid polling)
Or use the Counter component ( but uses interrupts)
Or use RTC (but internally it uses an interrupt, and only has 1-second resolution)
Thanks!
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PSOC5 LP MCU
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The standard Counter component does just that: it increments internal register value by 1 on each clock rising edge. If clock frequency is 1kHz then counter is incremented each millisecond.
On the other hand, the counter period is rather long (1ms), which can be handled by interrupt as well if other procsses don't load CPU heavily. It may have some benefits if Deep Sleep is required
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The standard Counter component does just that: it increments internal register value by 1 on each clock rising edge. If clock frequency is 1kHz then counter is incremented each millisecond.
On the other hand, the counter period is rather long (1ms), which can be handled by interrupt as well if other procsses don't load CPU heavily. It may have some benefits if Deep Sleep is required
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Thanks. I didn't know that the Counter worked like that 🙂
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ricardo,
It appears you are familiar with many of the PsoC timer options.
I understand you want to avoid diverting the CPU with an interrupt.
What I don't understand is the statement:
I'd like to avoid calling an ISR every millisecond just [to (sic)] update a variable.
Help us to understand your requirements. This will allow the forum to provide an optimum solution.
Questions:
- How often does the variable need to be updated?
- Is this variable computed (needing the CPU) or can it be derived by a HW method such as a LUT (Look Up Table)?
- What is the risk if the variable cannot be updated in time? (ie CPU too busy doing something else) Polling avoids the ISR but depending on the application being run, the sub-task of updating the variable is less guaranteed to process the variable in a timely manner.
The PSoC5 is a great uC in that it can use HW state machines to perform very complex functions WITHOUT virtually any CPU intervention. This unloads the CPU for potentially high-speed operation.
Even the DMA resources available are quite substantial so that extremely minimal CPU clock cycles are used to move data.
If the variable can be updated relatively simply, then a Look-Up-Table might do the trick on the event clock you desire.
"Engineering is an Art. The Art of Compromise."
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Thanks Len. The "Counter" module is exactly what I needed.