During a reset the chip is inoperable for a short time. This WILL affect your hardware logic.
After a "normal" reset (and after an internal watchdog reset, too) all the pins go into high-z. Then the internall logic gets re-configured from data in flash and the pins are set to their programmed state. This process will take some significant time.
On the other hand, a pure software reset could be done by setting the stack to a pre-defined value and loading the pc (program-counter) with the main() address (including some flag resets). This can be done in software.
So my suggestion would be to use an internal timer LIKE a watchdog that resets only the software leaving the hardwate untouched (as long as it is not proved inoperable).
As long as you do not reset your PSoC your hardware logic WILL run. So the question arises how to make your software rainproof. There are methods for that, ie EVERY function returns, at least after a specified time or number of tries, reporting back success or failure. so no "hanging" will occur. "Deadlock" is a different situation where more than one independent processes try to acquire resources which are already in use by other processes. There are cures against that situation.
Software can be made error-free or at least made in a way that it is recognizing its own errors and handling them appropiately. So you should trust in the deterministic behaveour of todays processors as you already trust in the deterministic behaveour of programmable logic.
The Watchdog does not power down system, so Verilog solution comes to mind.
The only issue I see is GPIO initialization on reboot (vs reset), are there any effects
produced by a Watchdog exception on restart. And could the Verilog solution
detect a Watchdog exception and reset its GPIO needed after a timeout of sorts.
You might file a case and ask staff -
"Create a Case"