I have a question regarding PLD power draw, particularly digital blocks with a very slow (or no) clock.
I have an application I'm considering porting to PSOC, but before I do I'd like to hear what the consensus is about running PLD blocks in very low power designs.
The design needs to sleep for the majority of its lifetime as it is battery powered, and must last several years. the device wakes up roughly once every second for about 1ms, and should have an average power draw below 40uA.
I now want to extend the device to incorporate a receiver for a very low data-rate serial protocol. essentially the receiver device will send a wake signal to its micro, followed by a clocked data stream of about 2ms per bit (500 baud). Capturing the data is very easy. In my current micro implementation I sample the data with an interrupt triggered by the clock line. The problem with this is power. As it is currently I have to keep my micro awake for the entire duration of the data transfer (~100ms), which basically kills any aspirations I have for a lower power device.
I thought the project might be a good candidate for a PSoC, as I could use an SPI block or even a custom Verilog based block to capture the data, and wake my micro a fixed timeout period after the data has stopped.
My question is, will a psoc PLD block draw little enough current if it has a very slow (just the 2ms data clock line, perhaps a 32khz source for timeout...). Can I even have PLD blocks running in sleep modes? Would it be more effective to have the micro simply wake briefly every time the clock line activates?
Thanks for the reply.
I read the low power app notes again, but they aren't very clear regarding the digital blocks. I noticed the bits in the table about "retention mode" for the UDB blocks, and I'm not really sure if this is simply a consequence of them being utlilsed with a MHz clock (which I can understand will stop) or is there some part of them that is intrinsically disabled? They also refer to 'digital blocks' and Im not sure what they mean by that.
let me state it simply:
1. If I connect 2 inputs and one output to an asynchronous element like an AND gate and put my psoc in deep sleep, will the AND gate continue to unction as expected?
2. If I have a shift register capturing data on one pin, using a clock from another pin (and no other clock source), will it still capture data in sleep/dep sleep modes?
3. If I were to power a digital block like a UDB based timer from the ILO clock, will it continue to run in sleep (assuming the ILO is correclty configured to run during sleep)
Thanks in advance for any help.
Just a thought, try a quick test, thats the beauty of PSOC you can
do a lot of self testing quickly just doing a test project. I agree docs
a little thin, you can always file a CASE -
To create a technical case at Cypress -
“Create a Case”
You have to be registered on Cypress web site first.
Neither the AND-gate nor the output you may connect the gate to will work in deep sleep.
In deep sleep mode only the interrupt controller, ILO, LP-comparators and WDT get powered. (Maybe I've forgotten one or two things like the low-voltage interrupt)
PSoC 4000 supports Sleep and Deep-Sleep modes. In
Sleep mode, GPIOs are active and can be actively driven
by peripherals, such as CapSense, TCPWM, and I
2C. In Deep-Sleep mode, pin states are latched to retain the
output state. I2C pins, however, are functional and can
wake up the device on an address match event. GPIO
interrupts are available in both the modes.
You could use an UART for the data transmission which will use 9µA @ 100kBit/s. Wakeup for the transfer could be done with an input pin that gets the PSoC out of deep-sleep. As said before, the GPIO interrupt is still active in this mode.
Has somebody already found the specs how much current the PSoC4 draws in deep-sleep?
For whatever reason I thought this whole thread was PSOC 4. So
power consumption posted from PSOC 4 datasheet, which is irrelevant
to PSOC 5LP.