You calculate CRC, from a stream , and after this there isn't any compare with crc incoming and the calculate.WhY they put a CRC calculation, for platonic view?
In same manner , in PRS module, they remove compare function as exist in PSOC1, and if i want compare one random number with the value coming for example from a serial stream ?. another platonic and unuseful things.
In the same manner for the shith register or others logic there isn't compare logic.
The bad things that exist in PSOC1, take a look on PRS module, that it's easy to transform in a shifth register..
Using Warp verilog it's like take an hammer and punch it's feet.
I like known , the reason for forget this important logic function ?, that complete like said before CRC, PRS and others module.
The CRC usermodule calculates the CRC value of the input bit stream as long as the UM is enabled and clock pulses are supplied. Conventionally, the input bit stream also comprises of thr CRC bits as well, so that the receiver can verify the calculated CRC with the received one. In the case of the usermodule, you can do this compare by allowing the CRC usermodule to read in all the data (including CRC bits), and then reading the calculated value using CRC16_ReadCRC function. If the values match, it should return a "0" value. (the final 16 CRC bits received) XORed with (the calculated value) = 0 if matched}
The same technique can be applied to other UMs that use shift registers. (PRS16_wReadPRS for PRS usermodule)
If you are looking at making a specific fuinction, please look into the Digital Communication Block (DCB) architecture from the PSoC 1 technical reference manual. It should help you understand the scope of the hardware.