The entire digital cuircuit consumes around 60% of all avaliable UDP blocks and unique Pterms. When I add the control registers the number increases dramatically so that the resources available on the chip are not enough. Is there a way for me to deal with this?
Can you share the project so far, or perhaps drag a schematic to your post? I'm imagining some logic or multiplexer configurations but I don't know what to suggest unless we hear what you need to accomplish.
This is most likely the delinquent component (I won't be posting the entire projects because it has quite a few layers of abstraction).
Essentially, what needs to happen here is: 'Active' input going high for a short pulse, should produce 7 short pulses, each delayed by an individually configurable number of clock cycles.
All the mentioned registers would be outside this component connecting to 'shift_1' - 'shift_7' inputs.
A digital comparator (configured for equals) needs 3 macrocells each, so your 7 comparators need 21 macro cells (out of 192 available ones). You need one macro cell for the DFF, and some of the PLD resources for the logic (lets say 2 PLD blocks, so one UDB). The BasicCounter needs another 8 MCs
the control registers don't need macro cells, but use the control register in an UDB (so you use 12 of the 24).
My guess is that the routing between all the elements of your design (since you say its much larger) needs to much of the additional PLD resources. You can look at the report file (*.rpt) what resources are consumed, and where this happens.
One solution might be to utilize the Datapath for your logic.
You could probably program the comparision into a single UDB using some of its internal registers. A control reg is not needed since the registers can be written by the CPU directly. Not a 5-minute job, but can be done in verilog.
The datapath is limited to -
Might not be enough, and general, to do what you want. Unless general UDB accessable memory
What is -
1) Rep rate and width of input pulse, range min to max both rate and PW ?
2) Resolution of delay (8 bits I assume) ?
a. Confirm output PW rep rate same as input.
3) Characteristics of output pulse (eg. PW.....duty cycle.....)
Thank you for the input everyone. I finally managed to achieve the functionality I wanted by implementing a counter+comparator with a CPU-definable compare-to value, using one datapath and one UDB block. There's enough of them to replace each comparator present in my initial design and they don't consume nearly as much resources!
Congratulations to get it working! Yes, a Datapath can replace many single gates, its a small CPU after all.