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PSoC 5, 3 & 1

Anonymous
Not applicable

I want to produce a multiphase voltage wave using VDAC’s and Timers. The included figure shows the waveform that I’m trying to create.  T1-T4 represent timings of each phase.

   

   

                   

   

I’ve had some success creating the waveform using one timer, two VDAC’s, and an AMuxSeq. I used two VDAC’s and a mux in efforts to make sure the rise and fall time of the phases were sharp (this may be an incorrect assumption). My project cannot create different values for T1-T4. Should I wire 4 timers together or simply sequentially start/stop a different timer for each phase?

   

Can someone help me build a efficient timing scheme for creating different durations values for each phase?

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1 Solution
HeLi_263931
Honored Contributor II

You can use the 'normal' wave generator strategy - driving the DAC from the DMA. See the WaveDAC8 AppNote for an example: http://www.cypress.com/?rID=54728 . You would need to modify the waveform stored in the RAM to match your timings.

View solution in original post

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28 Replies
Anonymous
Not applicable

Here's my current project file.

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Bob_Marlowe
Expert II

I think it depends on how precise our times have to be reproduced and how long your time phases are.

   

When the frequency is low enough, you could do with just one timer and one DAC. the trick is to set up everything after a phase change for the next phase and using the strobe input of the DAC from the (single) timer TC.

   

If frequency is too high, I would suggest to use a PWM which is able to generate two of your phases and with chance even all four.

   

Bob

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HeLi_263931
Honored Contributor II

You can use the 'normal' wave generator strategy - driving the DAC from the DMA. See the WaveDAC8 AppNote for an example: http://www.cypress.com/?rID=54728 . You would need to modify the waveform stored in the RAM to match your timings.

View solution in original post

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ETRO_SSN583
Esteemed Contributor

Some thoughts -

   

 

   

1) You have built a constant I generator to drive load, with switches to reverse polarity,

   

but that is not reflected in timing diagram, so not sure of its purpose ?

   

 

   

2) Your description is that all pulses occur sequentially, so I only see the need to use one VDAC.

   

 

   

3) Prior thread, ram based table makes good sense if this is a repetitive waveform. Store in table

   

wave amplitude, width, and at each terminating PWM pulse, ISR, do the next lookups and write

   

the VDAC and PWM period, duty cycle registers.

   

 

   

Regards, Dana.

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Bob_Marlowe
Expert II

Or, following Dana's advice, use DMA to keep the CPU free from doing too much work. There is a WAVEDAC component using this feature (run a keyword search on that). If you still in need of a solution I'll have to dig for an example I programmed using a table in Rom sending out data to a DAC repeatedly.

   

Happy DACing

   

Bob

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ETRO_SSN583
Esteemed Contributor
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Anonymous
Not applicable

The range of timing values for T1, T2, and T3 are between 0.3 - 10 milliseconds.

   

Danaaknight:

   

1) Yes, the purpose of the voltage signal is to control an external constant current generator (see image). The non-zero phases will be able to have their polarity switched. In the end I will need to control the exteranal analog switching using the PSoC timing scheme.

   

2) Yes, the pulses occur sequentially.

   

3) As I mentioned, I am considering the analog switching scheme in efforts to create a waveform with fast rise and fall times. My concern is that using one VDAC is that it isn't fast enough to change values before the switch changes polarity.

   

Bob:

   

There may be no time delay between the two non-zero phases in some instances (T2=0). Thus, I will have no time between the two non-zero phases. T4 represents the delay between repeats of the waveform.

   

 

   

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ETRO_SSN583
Esteemed Contributor

Now I understand, I thought the original goal was a wide dynamic range of

   

setting amplitude, its clear you only need limited number of voltages. Excellent

   

approach using muxed fixed voltages.

   

 

   

Note the OP162 has limited C load capability, hence phase margin, because

   

the MAX4622 presents a lot of Cload, thats why it has such good Ron for an

   

analog swtitch, lots of channel, hence Miller. Look at datasheet, there is a

   

section on loading to handle the phase margin problem in the 162 to keep

   

the ringing down.

   

 

   

Regards, Dana.

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HeLi_263931
Honored Contributor II

According to the data sheet, the VDAC has a settling time of 1µs max, in the 1V range (the typical value is 0.45µs). If this is enough, the DAC solution is viable. If not, the idea with the fixed voltages is fine.

   

If you want to have a more hardware-based solution, you need to use 4 timers (one for each period). You can trigger them in a linked ring (t1 trigeers T2, T2 trigger T3 and so on), and with each trigger event you can use a lookup table to select the proper output on your mux.

   

If you want to use only a single timer, you could use a DMA to set the timer periods. Each timer a timer reaches its TC, switches to the next output via the lookup table, triggers the DMA event to write the next period values, and the starts the timer again. (Though I think that this will get tricky)

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ETRO_SSN583
Esteemed Contributor

If the "bit" timing is same, pulse to pulse, a single LUT can

   

provide triggers and timing. I know the diagram does not in-

   

dicate this, but if it were.........

   

 

   

Regards, Dana.

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HeLi_263931
Honored Contributor II

Btw: I think we should ask Dave for some official 'PSoC zealot' T-Shirts: we got already 5 different solutions for the same problem 🙂

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Bob_Marlowe
Expert II

Are those shirts available in XXXL?

   

Bob

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HeLi_263931
Honored Contributor II

When I stay with my preconceptions about the US: when Dave wears a XL shirt, it means XXXL in Germany 🙂

   

(Though I'm afraid that after this statement I will never receive such a shirt...)

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Bob_Marlowe
Expert II

OK, so XXXL in US is a tent, but I know, I'm a bit more in size than Dave.

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HeLi_263931
Honored Contributor II

Then just send him one of yours, challenge him to wear it on PSoC Today, and ask for another one back 🙂

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Anonymous
Not applicable

Is there any way I could estimate the time it takes to switch between phases using one VDAC? I know the settling time and rise/fall time of the VDAC are listed in the documentation. What about the time it takes to handle the ISR's and execute any code or API function calls. I can't find any documentiontation about the number of clock cycles required for specific API's (i.e. - VDAC8_SetValue() ).

   

 

   

I may be over analyzing this, but I don't want to find out later that my design is too limited by the time required for code/API execution.

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Bob_Marlowe
Expert II

Since the switching occurs for every signal change, as long as your program paths within the isr do not differ too much it will induce only a phase-shift to your output-signal.

   

 

   

Bob

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ETRO_SSN583
Esteemed Contributor

You can synch the Timer update to the VDAC update, that then leaves the settling time

   

of the VDAC as the main limiting delta between start of timer period and final amplitude

   

for that period. Note there is uncertainty to Timer start that also has to be factored in.The

   

VDAC settling time is speced in data sheet for Cload and different ranges. You could delay

   

the timer start by that settling time, although that spec has a lot of variance device to device,

   

and temperature. Alternatively you could develop a cal routine to test the "pedestal" problem

   

and compensate clock delay to start Timer.

   

 

   

 

   

I am curious why you abandoned mux approach with a VDAC ? Did you need more

   

amplitude step resolution ? I would venture that settling time of Mux followed by Buffer

   

is < VDAC settling time, worth a test bench examination to see if that is true.

   

 

   

 

   

There is an ap note on analog routing, which gives you path R that allows you to get

   

an estimate of AMUX delay/settling, as that datasheet has no settling specs. Its crude

   

but better than nothing. AN58304.

   

 

   

 

   

Regards, Dana.

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Anonymous
Not applicable

I did some bench testing on a few designs that use one timer and either one or two VDAC's. See the table below and/or the attached pdf file. Any comments on the resluts are very welcome!!

   

 

   

I believe the timing and duration control of the different waveform phases were accurate enough for my needs in all the designs. The design that had the fastest rise and fall time was a design submitted to me from a Cypress tech. Their design uses a digital output pin and a control register as some kind of switch and drive scheme. I don't completely understand it, but it works. However, going from 4V to 0V there is significant ringing in the waveform (see pdf). I'm not sure why. Adding a buffer did not change anything.

   

 

   

                   

                                                                                                                                                                                                                                                             
     Rise/Fall Time Comparison    

Design

Rise Time (µs)

Fall Time (µs)

1xVDAC > No Buffer

6.0

6.0

1xVDAC >Buffer

0.75

0.78

1xVDAC > AMuxSeq > Buffer

0.78

0.80

2xVDAC > AMuxSeq > Buffer

0.76

0.88

2xVDAC > AMuxSeq > No Buffer

6.0

0.2

1xVDAC > Digital Output Pin w/ Control Register

0.04

0.008

   

                    Notes: VDAC’s and buffers were in fast mode. Digital pin was set to strong drive mode and drive level to Vref. Rise and fall times were computed between 10% and 90% full range during a 4V waveform phase. Vdd was 5V. One timer was used for all designs.

   

 

   

Questions:

   

(1) Why did the AMuxSeq designs not have better times than the designs using only VDAC's? Was I not accounting for something in the signal chain to my scope?

   

(2) Could someone help explain how the digital output pin with control register design works exactly?

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Anonymous
Not applicable

Here's the design that uses a digital output pin and control register.

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Anonymous
Not applicable
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ETRO_SSN583
Esteemed Contributor

See attached picture of output reference generator associate with SIO pins. That

   

explains how the output drives to the Vref level.

   

 

   

Ringing, thats the I/O driving Cload, and effect on VDAC output. Some relief

   

can be had by setting output to slow slew rate, or adding a small R to the output pin.

   

You could add a small R and C to VDAC out, C to act as power source, R to isolate

   

VDAC from lthe cap, basically try these as possibilities.

   

 

   

Regards, Dana.

ETRO_SSN583
Esteemed Contributor

One other comment, generally speaking when you see a lot of ringing it

   

is either inductance-capacitiance produced (obvious) or phase margin

   

in an active element, like an OpAmp. In the later it also indicates, because

   

the phase margin is too small, you are close to oscillation. So always pay

   

attention to curing this because device to device variations can bag you on

   

this.

   

 

   

Regards, Dana.

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ETRO_SSN583
Esteemed Contributor

I also suspected range of Vout would be limited, spec shows this -

   

 

   

See attached -

   

 

   

Regards, Dana.

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ETRO_SSN583
Esteemed Contributor

I looked at this on a PSOC CY8CKIT-030, and saw no ringing. I then also did it in

   

infinite persistance mode, nothing there either. I then ran design at  a double pulse

   

width of ~ 40 uS, some undershoot, and Tf ringing here settled in about 20 nS.

   

 

   

Some thoughts -

   

 

   

1) Are you using a 1X probe, usually has a lot of C vs a 10X probe.

   

2) Go thru the cal routine in the scope for probes.

   

3) Do you see a lot of ringing on Vdd, main power supply ? Thats an indication

   

of inferior bypass caps. .1 uF ceramic disc close to part as well as bulk cap.

   

4) Scope probe ground lead excessively long, > 4" ? That makes for a lot of L.

   

5) Bulk tantalum, consider newer Polymer parts, they have an order of magnitude better

   

freq response curve.

   

 

   

My earlier suggestion on R and C, that will affect Tr and Tf in the design, as a compromise to get rid of ringing.

   

 

   

Regards, Dana.

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HeLi_263931
Honored Contributor II

When you don't use a buffer, the internal resistance of the analog paths will limit the rise and fall times. I think it might be easily around 600 to 1000 ohm (you can look with the analog design viewer what it is exactly). But when you use a buffer, you have a low resistance path to the dedicated output pins. The slew rate is also affected by the capacitance of the attached peripherals.

   

One question: when you use the digital output pins, how do you create the different voltage level? Or did you do that just for comparing how fast the output can be?

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Anonymous
Not applicable

danaaknight: I was using a 1x probe. I changed to a 10x probe and the ringing was reduced. My scope's inputs are 1Mohm/15pF. I added a 220 ohm resistor and the ringing dissappeard. I am using the PSOC CY8CKIT-030 also, and don't see any significant ringing in the Vdd.

   

hli: I use a timer and ISR to change the voltage of a VDAC. The VDAC is then connected to the digital pin's Vref terminal (see image). Switching of the pin on/off is controlled by a control register, timer, and ISR. I attached the project on a previous post.

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ETRO_SSN583
Esteemed Contributor

Looks like you have this under control.

   

 

   

I had not realized I/O on SIO had this feature, too bad its not on the

   

rest of the GPIO. Vref generator.

   

 

   

The only limitation on this is the active switch used for pullup to Vdd in the output

   

structure. Because its got source bulk effect raising its Vth you have a min amplitude

   

limit on your output pulse.

   

 

   

One last comment, this is application specific, but generally killing ringing with unit loads,

   

clocks, etc., only takes 20 ohms, just curious.

   

 

   

Regards, Dana.

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