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PSoC 5, 3 & 1

HuEl_264296
New Contributor II

I am creating a Verilog component which requires a clock. I would like this to be an internal clock, so that the user doesn't need to concern themselves with it.

   

 

   

I have seen some components (eg PWM) which have the option of an internal clock. This is implemented by using a schematic component containing the clock plus another verilog component.

   

 

   

Is it possible instead to simply instantiate a clock within the Verilog?

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2 Replies
HeLi_263931
Honored Contributor II

AFAIK you need the external clock. This is because PSoC needs to allocate a clock resource for that (e.g. a divider), and this is something separate from the UDB. So you will need a schematic component for that.

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Bob_Marlowe
Expert II

There is no VeriLog instruction that creates a clock and sets its frequency, Easiest would be to connect a clock to your component and use that a s a macro or wrap it into a schematic component.

   

 

   

Bob

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