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PSoC™ 5, 3 & 1

hitac_1138561
New Contributor

Our circuit which wants to come out is PWM display constructed at a counter of the one-shot setting.

The following figures are the circuit and setting information.

無題.png

無題2.png

無題3.png

In addition, the comparison is set by software as follows.

     Counter_1_Start();

     Counter_1_WriteCompare(n);    /* n=0...255 */

In our environment, COUNTER does not begin to run.

I want us to point out the point where a problem lies hidden in.

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1 Solution
MotooTanaka
Esteemed Contributor

Hi,

So I think we came as far as we could get with 8bit  counter.

And if you really need 255 equality, we need a counter with more than 8bit width.

Probably using a 16bit mode or create a 9~bit UDB one.

Anyway, at least a good news is the counter itself seems working 😉

moto

View solution in original post

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5 Replies
jowoc_4081536
New Contributor

Hi!

I thank for having had you show your design and think that it is very interesting.

It is a device to let you maintain an RUN state of COUNTER to have attracted

interest in particular.

I intend to perform an experiment for confirmation from now on.

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jowoc_4081536
New Contributor

I will report my confirmation results.

compare value = 255

0000.jpg

Like an original circuit, I come to be able to set COMPARE_VALUE to 255 by making CLOCK_MODE DOWN_COUNTER.

However, the PIN_1 output cannot output 255 equally because ENABLE period is confined to 254.

This circuit seems to work normally.

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MotooTanaka
Esteemed Contributor

Hi,

So I think we came as far as we could get with 8bit  counter.

And if you really need 255 equality, we need a counter with more than 8bit width.

Probably using a 16bit mode or create a 9~bit UDB one.

Anyway, at least a good news is the counter itself seems working 😉

moto

View solution in original post

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hitac_1138561
New Contributor

I thank the people who answered.  Thank you, MOTO.  Thank you, JW.

As a result, this counter works definitely now in my environment.  It was a difficult part

to think of the cause of COUNTER not having worked.  The counter has begun to work

by decreasing system clock frequency.  Because I used up UDB approximately 100%

by my design, it seemed to happen.

This clock signal does not exist in the connection diagram which I showed in this matter.

I will do the detailed report about this matter with another opportunity.

I helped that the inspection contents of all of you discovered a cause early.

Thank you again.

MotooTanaka
Esteemed Contributor

Hi,

I tried with following schematic.

004-schematic.JPG

But when I tried to set the period to 255, I got error saying that the allowed range is 1 to 254.

001-message.JPG

So I set the period to 254

002-254.JPG

On my oscilloscope

ch1 : cntr_reset

ch2 : comp

ch3 : ENABLE

ch4 : Pixel_clock

When I set compare value to 0

i=0.JPG

compare value = 10

i=10.JPG

compare value = 100

i=100.JPG

compare value = 254

i=254.JPG

compare value = 255

i=255.JPG

So, when I set the period to 254, the circuit seems to be working.

Meantime, with current PSoC Creator, I could not set the period to 255,

so may be setting the period to 255, which seems to be allowed earlier,

was the problem.

moto

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