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PSoC 5, 3 & 1

HeGr_603241
New Contributor

Hello,

I would like to select a CPU for an application and by chance I found the PSOC series. Question - description:

the CPU should run in a power-saving mode in battery operation, if possible for 3 to 4 years, and sample + count a quadrature signal (2 bits). The sampling of the quadrature signal should also be sampled in full operating mode and counted in real time.

Option 1: it is possible to use the quadrature encoder interface of the UDPs in power-saving mode (max. 12µA). So the interface could be used in the energy saving mode and also in full operating mode.

or

Variant 2: an RTC in sleep mode with approx. 500Hz INT frequency. Evaluation of the 2-bit inputs, counters of the UDP manually increment / decrement or read / change / write back. Quadrature encoder in normal operating mode.

Is variant 1 possible?

Regards

Heiko

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1 Solution
odissey1
Honored Contributor II

HeGr,

As Leonard Poma mentioned above, you can put PSoC into Deep Sleep mode, waking up only on Pin interrupt. Then read Pins state, update the encoder counter and go to sleep again.

The wake-up time from Deep sleep is short (25us), so average current should be small. See this blog as an example of the PSoC4 DeepSleep current measurement

https://iotexpert.com/2017/12/14/psoc-4200m-low-power-with-wdts/

To realize quadrature decoder in code (no UDBs), using interrupts or polling technique, please check this custom component

Quad Decoder with Button Switch component for rotary shaft encoders

Te interrupt code consumes about 50 processor clocks, after which it can go back to sleep again until next the interrupt

/odissey1

View solution in original post

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4 Replies
Len_CONSULTRON
Honored Contributor II

Heiko,

Regarding Variant 1:

It is unclear to me whether the UDBs used for the Quadrature encoder can be selectively left on in a lower power mode.

I have the PSoC5LP Power Mode App Note and it makes no mention of whether the state and logic of the UDBs can remain powered AND OPEARTIONAL in lower power modes.

https://www.cypress.com/documentation/application-notes/an77900-psoc-3-and-psoc-5lp-low-power-modes-...

Cypress will have to weigh in on this.

There is reference to the API calls to allow the component to go to Sleep (which is not what you want anyway).

Regarding Variant 2:

I believe this is achievable.

Len

Len
"Engineering is an Art. The Art of Compromise."
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odissey1
Honored Contributor II

HeGr,

As Leonard Poma mentioned above, you can put PSoC into Deep Sleep mode, waking up only on Pin interrupt. Then read Pins state, update the encoder counter and go to sleep again.

The wake-up time from Deep sleep is short (25us), so average current should be small. See this blog as an example of the PSoC4 DeepSleep current measurement

https://iotexpert.com/2017/12/14/psoc-4200m-low-power-with-wdts/

To realize quadrature decoder in code (no UDBs), using interrupts or polling technique, please check this custom component

Quad Decoder with Button Switch component for rotary shaft encoders

Te interrupt code consumes about 50 processor clocks, after which it can go back to sleep again until next the interrupt

/odissey1

View solution in original post

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odissey1
Honored Contributor II

HeGr,

I believe that the UDB solution (1) is not possible, as in Deep Sleep mode UDBs are disabled. There are some fixed-function periferals available (like UART), but not QuadDecoder. See, for example, this thread and links inside

Re: Periodly wakeup from deep sleep mode

/odissey1

PSOC 4 and BLE Sleep Mode Tables_0.jpg

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odissey1
Honored Contributor II

HeGr,

Last bit not least, you have to ensure that the encoder itself consumes no more than few uA itself, which means that some high reliability mechanical encoder with ~1M pull-up resistors should be employed.

In lew of the battery you may also consider harvesting energy of the mechanical source, which drives the encoder.

/odissey1

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