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PSoC 5, 3 & 1

SaKu_291986
New Contributor II

I want to run PSoC5LP Delsig at 12 bits / 20kHz sample rate, continuous conversion mode. What is the clock frequency required at an accuracy of 0ppm, if I use an external clock to the DelSig.

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1 Solution
NoriakiT_91
Employee

For example when the PLL output is set to 32MHz,

GS004802.png

The internal clock for ADC becomes 640kHz by dividing the 32MHz MASTER clock by 50.

GS004805.png

Now the actual conv. rate is 20000

GS004804.png

Regards,

Noriaki

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5 Replies
NoriakiT_91
Employee

In the configuration Utility window of a ADC_DelSig component, the required clock frequency is calculated from the give parameters.

GS004800.png

In this case, 640kHz clock is required.

Regards,

Noriaki

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SaKu_291986
New Contributor II

Thank you very much Noriaki-san. But what will I need to do, if I require that actual conversion rate to be 20,000Hz and not 20,834Hz?

Best regards,

Sampath

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NoriakiT_91
Employee

For example when the PLL output is set to 32MHz,

GS004802.png

The internal clock for ADC becomes 640kHz by dividing the 32MHz MASTER clock by 50.

GS004805.png

Now the actual conv. rate is 20000

GS004804.png

Regards,

Noriaki

View solution in original post

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odissey1
Honored Contributor II

SaKu,

With the above settings you can set ADC resolution to 16-bit, and get more accurate result for free, since you will be reading result using 16-bit variable anyway.

/odissey1

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